公开(公告)号：US08629721B2

公开(公告)日：2014-01-14

申请号：US13333862

申请日：2011-12-21

Applicant: Dimitri Soussan ,  Sylvain Majcherczak

Inventor： Dimitri Soussan ,  Sylvain Majcherczak

IPC: H03F3/16 ,  H03F3/26

CPC classification number: H03F3/2171 ,  H03F2200/387 ,  H03K17/04123 ,  H03K17/302 ,  H03K19/01721 ,  H03K2217/0018

Abstract: A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.

Abstract translation: 一种用于控制输出放大级的方法，包括在第一和第二电源轨之间串联的第一和第二互补SOI型功率MOS晶体管，该方法包括以下步骤：当第一和第二互补SOI型功率MOS晶体管的大部分连接到第一导轨时， 第一晶体管保持在断开状态; 当所述第二晶体管保持在断开状态时，将所述第二晶体管的主体连接到所述第二轨道; 并且在该晶体管从截止状态切换到导通状态的期间，将每个晶体管的大部分连接到所述晶体管的公共节点。

公开(公告)号：US08607630B2

公开(公告)日：2013-12-17

申请号：US12680687

申请日：2008-10-08

Applicant: Fabrice Casset

Inventor： Fabrice Casset

IPC: G01C19/00

CPC classification number: H03H9/02259 ,  H03H3/0072 ,  H03H9/2436 ,  H03H9/2463 ,  H03H2009/02496 ,  H03H2009/02503

Abstract: A vibrating nano-scale or micro-scale electromechanical component including a vibrating mechanical element that cooperates with at least one detection electrode. The detection electrode is flexible and is configured to vibrate in phase opposition relative to the vibrating mechanical element. Such a component may find, for example, application to resonators or motion sensors.

Abstract translation: 振动纳米尺度或微尺度机电部件，其包括与至少一个检测电极配合的振动机械元件。 检测电极是柔性的并且被配置成相对于振动机械元件相对振动。 这样的组件可以发现例如应用于谐振器或运动传感器。

公开(公告)号：US08593234B2

公开(公告)日：2013-11-26

申请号：US12896361

申请日：2010-10-01

Applicant: Pierre Bar ,  Sylvain Joblot ,  David Petit ,  Jean-Francois Carpentier

Inventor： Pierre Bar ,  Sylvain Joblot ,  David Petit ,  Jean-Francois Carpentier

IPC: H03H9/15 ,  H03H9/05 ,  H03H9/54

CPC classification number: H03H3/02 ,  H03H9/175 ,  H03H2003/025

Abstract: A method for manufacturing a bulk acoustic wave resonator, each resonator including: above a substrate, a piezoelectric resonator, and next to the piezoelectric resonator, a contact pad connected to an electrode of the piezoelectric resonator; and, between the piezoelectric resonator and the substrate, a Bragg mirror including at least one conductive layer extending between the pad and the substrate and at least one upper silicon oxide layer extending between the pad and the substrate, the method including the steps of: depositing the upper silicon oxide layer; and decreasing the thickness unevenness of the upper silicon oxide layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each pad.

Abstract translation: 一种制造体声波谐振器的方法，每个谐振器包括：在基板上方，压电谐振器上方，并且紧邻压电谐振器，连接到压电谐振器的电极的接触焊盘; 并且在所述压电谐振器和所述基板之间，布拉格反射镜包括在所述焊盘和所述衬底之间延伸的至少一个导电层和在所述焊盘和所述衬底之间延伸的至少一个上部氧化硅层，所述方法包括以下步骤： 上氧化硅层; 并且由于沉积方法而减小上部氧化硅层的厚度不均匀性，使得该层在每个焊盘的水平处具有相同的厚度，优于2％以内，优选在1％以内。

公开(公告)号：US08570096B2

公开(公告)日：2013-10-29

申请号：US13232529

申请日：2011-09-14

Applicant: Julien Le Coz ,  Alexandre Valentian ,  Philippe Flatresse ,  Sylvain Engels

Inventor： Julien Le Coz ,  Alexandre Valentian ,  Philippe Flatresse ,  Sylvain Engels

IPC: G05F1/10

CPC classification number: G05F3/205 ,  H03K19/0013

Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Abstract translation: MOS功率晶体管的衬底的动态偏置电路可以包括第一开关，其被配置为当晶体管的栅极电压使晶体管导通时，将衬底连接到电流源，该电流源向前偏置晶体管的本征源极 - 衬底二极管 。 电流源可以包括与衬底和电源电压之间的本征二极管相同的导通方向的二极管堆叠。

公开(公告)号：US20130270649A1

公开(公告)日：2013-10-17

申请号：US13859341

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Alain Chantre ,  Pascal Chevalier ,  Gregory Avenier

IPC: H01L29/73 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/7322 ,  H01L29/7371

Abstract: A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

Abstract translation: 一种制造双极晶体管的方法，包括以下步骤：形成半导体衬底的第一表面掺杂区，其半导体层在其上延伸有第一绝缘层; 在所述器件的表面处形成硅层和第二绝缘层的堆叠; 限定与所述堆叠交叉的沟槽和与所述第一掺杂区域相对的所述半导体层，以及所述第一绝缘层的所述暴露区域中的开口; 在开口中形成单晶硅区域; 在与所述半导体层和所述硅层的剩余区域接触的单晶硅区域的表面上形成硅 - 锗区域; 以及至少在所述沟槽的剩余空间中形成第二掺杂区域。

公开(公告)号：US20130201771A1

公开(公告)日：2013-08-08

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。

公开(公告)号：US08502574B2

公开(公告)日：2013-08-06

申请号：US13229478

申请日：2011-09-09

Applicant: Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

Inventor： Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0995 ,  H03L7/1974

Abstract: Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

Abstract translation: 用于生成包括参考信号的发生器的锁相环的参数化频率信号的装置，包括用于接收参考信号的第一输入的相位 - 频率比较器，基于由相位信号输出的结果输出的振荡器， 频率比较器，耦合在振荡器的输出和相位 - 频率比较器的第二输入端之间的分数分频器，以及选择器，选择性地将振荡器的输入与发生器的输入或振荡器的输出相连， 分数分频器的倍率的函数。

公开(公告)号：US08499228B2

公开(公告)日：2013-07-30

申请号：US12914306

申请日：2010-10-28

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/03

CPC classification number: G11B20/1803 ,  G11B2020/10759 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract translation: 一种方法是解码用纠错码编码并相互相关的N个信息项的块。 该方法包括执行块的N个信息项的第一去相关，并且存储相关的块。 该方法还包括执行用于解码该块的P个信息项的处理，以及对至少部分的P个解码的信息项进行解相关。 用于解码P个信息项的组合和解相关的处理被重复，直到块的N个信息项已经被处理之前的不同的连续的P个信息项组，直到满足解码标准。

公开(公告)号：US08493252B2

公开(公告)日：2013-07-23

申请号：US13032115

申请日：2011-02-22

Applicant: Jean Gorisse ,  Andreia Cathelin ,  Andreas Kaiser ,  Eric Kerherve

Inventor： Jean Gorisse ,  Andreia Cathelin ,  Andreas Kaiser ,  Eric Kerherve

IPC: H03M1/84

CPC classification number: H03M1/1235 ,  H03M1/16

Abstract: A logarithmic analog to digital conversion method for an analog input signal includes a logarithmic amplification with progressive compression of the input signal delivering a sequence of several secondary analog signals. The trend of the values of at least some of the secondary signals is a function of the values of the analog input signal including regions corresponding to a linear trend of the secondary signals as a function of that of the input signal expressed in a logarithmic scale. The method also includes a comparison of at least some of the secondary signals of the sequence with a common reference signal whose value lies within each of regions, supplying a thermometric code information item, and a generation of a first digital word from the thermometric code information item.

Abstract translation: 用于模拟输入信号的对数模数转换方法包括对输入信号进行逐次压缩的对数放大，该输入信号提供多个次级模拟信号的序列。 至少一些次级信号的值的趋势是模拟输入信号的值的函数，该模拟输入信号包括与辅助信号的线性趋势相对应的区域作为以对数刻度表示的输入信号的函数的函数。 该方法还包括将序列中的至少一些辅助信号与其值位于每个区域内的公共参考信号进行比较，提供测温代码信息项，以及从测温代码信息生成第一数字字 项目。

公开(公告)号：US20130183774A1

公开(公告)日：2013-07-18

申请号：US13619583

申请日：2012-09-14

Applicant: Raphael Paulin ,  Patrice Garcia

Inventor： Raphael Paulin ,  Patrice Garcia

IPC: G01R31/26 ,  H01L21/66 ,  G06F19/00

CPC classification number: G01R31/2848 ,  G01R27/32 ,  G06F17/5036 ,  G06F17/5063

Abstract: A method for testing an integrated circuit includes determining performance data of the integrated circuit, wherein at least first and second derivatives of S parameters of the integrated circuit are taken into account when determining the expected performance data. The performance data can be determined by measuring S parameters of the integrated circuit. An equivalent non-linear model of the integrated circuit can be determined from the provided S parameters and first and second derivatives of the provided S parameters. The non-linear behavior of the integrated circuit can be quantified from the equivalent non-linear model.

Abstract translation: 一种用于测试集成电路的方法包括：确定集成电路的性能数据，其中在确定预期性能数据时考虑集成电路的S参数的至少第一和第二导数。 性能数据可以通过测量集成电路的S参数来确定。 可以从所提供的S参数和所提供的S参数的第一和第二导数来确定集成电路的等效非线性模型。 可以从等效非线性模型量化集成电路的非线性行为。