公开(公告)号：US20130339631A1

公开(公告)日：2013-12-19

申请号：US13909339

申请日：2013-06-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F12/00

CPC classification number: G06F13/4022 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/00 ,  G06F12/02 ,  G06F13/1657 ,  G06F13/1668 ,  G06F13/4282 ,  G11C5/02

Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

Abstract translation: 在数据处理系统中，缓冲器集成电路（IC）装置包括多个控制接口，多个存储器接口和切换电路，以根据路径选择值将每个控制接口同时耦合到相应的一个存储器接口。 多个请求者IC设备分别耦合到控制接口，并且多个存储器IC设备分别耦合到存储器接口。

公开(公告)号：US20130305079A1

公开(公告)日：2013-11-14

申请号：US13923656

申请日：2013-06-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G06F1/10

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component.

Abstract translation: 存储器组件具有信令接口，数据输入/输出（I / O）电路和命令/地址（CA）电路。 信令接口包括片上终端数据I / O和未终止的CA输入。 数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效 时间在数据I / O。 CA电路响应于第二时钟信号的上升沿和下降沿转换在CA输入端采样CA信号，CA信号指示要在存储器组件内执行的读和写操作。

公开(公告)号：US20130265842A1

公开(公告)日：2013-10-10

申请号：US13901014

申请日：2013-05-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G11C8/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract translation: 微线程存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。 提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和 最小访问时间间隔。

公开(公告)号：US20130194879A1

公开(公告)日：2013-08-01

申请号：US13712842

申请日：2012-12-12

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract translation: 根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

公开(公告)号：US08493802B1

公开(公告)日：2013-07-23

申请号：US13741255

申请日：2013-01-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10 ,  G06F12/00

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time.

Abstract translation: 存储器控制器将地址位和第一定时信号输出到DRAM，每个地址位与第一定时信号的边缘相关联，第一定时信号需要第一传播延迟时间传播到DRAM。 存储器控制器还与地址位相关联地向DRAM发送写数据位和第二定时信号，每个写数据位与第二定时信号的边沿相关联，第二定时信号需要第二传播延迟时间 传播到DRAM。 存储器控制器包括多个串联耦合的延迟元件，以提供相应的不同延迟的内部延迟定时信号;以及多路复用器，基于第一传播的差异来选择要输出的延迟定时信号之一作为第二定时信号 延迟时间和第二传播延迟时间。

公开(公告)号：US20130176800A1

公开(公告)日：2013-07-11

申请号：US13741255

申请日：2013-01-14

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time.

Abstract translation: 存储器控制器将地址位和第一定时信号输出到DRAM，每个地址位与第一定时信号的边缘相关联，第一定时信号需要第一传播延迟时间传播到DRAM。 存储器控制器还与地址位相关联地向DRAM发送写数据位和第二定时信号，每个写数据位与第二定时信号的边沿相关联，第二定时信号需要第二传播延迟时间 传播到DRAM。 存储器控制器包括多个串联耦合的延迟元件，以提供相应的不同延迟的内部延迟定时信号;以及多路复用器，基于第一传播的差异来选择要输出的延迟定时信号之一作为第二定时信号 延迟时间和第二传播延迟时间。

公开(公告)号：US20130064023A1

公开(公告)日：2013-03-14

申请号：US13670343

申请日：2012-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/22 ,  G11C7/00

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/409 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract translation: 存储器系统包括将数据写入存储器件并从存储器件读取数据的存储器控​​制器。 伴随写入数据的写入数据选通信号在写入数据有效时向存储器件指示，而伴随来自存储器件的数据的读取选通器在读取数据有效时向存储器控制器指示。 存储器控制器自适应地控制写入数据选通的相位以补偿存储器件的定时漂移。 存储器控制器使用读取信号作为漂移的度量。

公开(公告)号：US12223207B2

公开(公告)日：2025-02-11

申请号：US18487955

申请日：2023-10-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C29/02 ,  G11C29/04

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US12222829B2

公开(公告)日：2025-02-11

申请号：US18373219

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US12198780B2

公开(公告)日：2025-01-14

申请号：US18340803

申请日：2023-06-23

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G06F13/16 ,  G11C5/06 ,  G11C7/10

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.