公开(公告)号：US07859134B2

公开(公告)日：2010-12-28

申请号：US12005056

申请日：2007-12-21

申请人： Steve X. Chi ,  Yongliang Wang ,  Ekram Hossain Bhuiyan ,  Daniel P. Nguyen ,  Vincent Anthony Condito ,  Po-Shen Lai

发明人： Steve X. Chi ,  Yongliang Wang ,  Ekram Hossain Bhuiyan ,  Daniel P. Nguyen ,  Vincent Anthony Condito ,  Po-Shen Lai

IPC分类号： H02J1/00 ,  H02J3/00

CPC分类号： G06F1/26 ,  Y10T307/696

摘要： A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

摘要翻译： 一种用于操作具有专用半导体电路（ASIC）的电子产品的方法，该电子产品在其电路中包括与可选外部电容一起使用的线性调节器模块和耦合到产品的内部电容的无电容调节器模块，选择低功率子 模块或高功率子模块，用于ASIC的上电阶段。 ASIC的控制逻辑确定是否存在外部电容。 如果是这样，则在ASIC的上电阶段期间使用高功率无帽子模块; 如果不仅在ASIC的上电阶段期间使用低功率无帽子模块。 在ASIC上电之后，控制逻辑可以在某些操作时间内选择线性调节器模块，并在其他操作时间内选择无限幅调节器模块，或者可以在后期上电操作的所有时间中选择一个或另一个 。

公开(公告)号：US20100318839A1

公开(公告)日：2010-12-16

申请号：US12485846

申请日：2009-06-16

申请人： Chris Nga Yee Avila ,  Jonathan Hsu ,  Alexander Kwok-Tung Mak ,  Chen Jian ,  Grishma Shailesh Shah

发明人： Chris Nga Yee Avila ,  Jonathan Hsu ,  Alexander Kwok-Tung Mak ,  Chen Jian ,  Grishma Shailesh Shah

IPC分类号： G06F11/14 ,  G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0893 ,  G06F11/1433 ,  G06F11/1666 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/04 ,  G11C29/82 ,  G11C2211/5643

摘要： In a nonvolatile memory array, data is stored in multi-level cells (MLC) as upper-page data and lower-page data. Safe copies of both upper-page and lower-page data are stored in on-chip cache during programming. If a write fail occurs, data is recovered from on-chip cache. The controller does not have to maintain safe copies of data.

摘要翻译： 在非易失性存储器阵列中，将数据作为上层数据和下页数据存储在多级单元（MLC）中。 在编程期间，上页和下页数据的安全副本都存储在片上缓存中。 如果发生写入失败，则从片上缓存中恢复数据。 控制器不必维护数据的安全副本。

公开(公告)号：US07848149B2

公开(公告)日：2010-12-07

申请号：US11674000

申请日：2007-02-12

申请人： Carlos J. Gonzalez ,  Daniel C. Guterman

发明人： Carlos J. Gonzalez ,  Daniel C. Guterman

IPC分类号： G11C11/34

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C16/12 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2013/0057

摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.

摘要翻译： 存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。 可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。 这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。 可以在编程的验证阶段期间采用类似形式的信号平均。 该技术的实施例将使用峰值检测方案。 在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。 如果验证的一些预定部分失败，则存储元件接收另外的编程。 这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

公开(公告)号：US07848144B2

公开(公告)日：2010-12-07

申请号：US12139545

申请日：2008-06-16

申请人： Menahem Lasser

发明人： Menahem Lasser

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the word lines has a higher logical page address than any page that is written to a subsequently written word line, regardless of the sequence in which the pages are received for writing. Alternatively, the pages are written to the word lines so that for every pair of written word lines, the word line of the pair that is earlier in the writing order has written thereto a page having a higher logical page address than at least one page written to the other word line of the pair.

摘要翻译： 为了在字线写入顺序中连续写入字线的存储块中存储由逻辑页地址排序的多个数据页，将页写入字线，使得写入任何一行的每一页 一个字线具有比写入随后写入的字线的任何页更高的逻辑页地址，而不管页面被接收以写入的顺序。 或者，页面被写入字线，使得对于每对写入的字线，在写入顺序中较早的对中的字线已写入具有比至少一个页面写入的更高逻辑页地址的页面 到对的另一个字线。

公开(公告)号：US07830039B2

公开(公告)日：2010-11-09

申请号：US11965943

申请日：2007-12-28

申请人： Daniel P. Nguyen ,  Steve X. Chi

发明人： Daniel P. Nguyen ,  Steve X. Chi

IPC分类号： H02J7/00

CPC分类号： H03K17/223 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/50 ,  Y10T307/62 ,  Y10T307/696

摘要： Methods and systems for automatically and/or locally adjusting power-valid detection. In one class of embodiments, local power-on-reset circuits are included in individual power islands; in another class of embodiments, the power-on-reset circuit is automatically reprogrammed, depending on the detected interface voltage level, to use the same circuitry for power-valid detection in either case.

摘要翻译： 用于自动和/或本地调整功率有效检测的方法和系统。 在一类实施例中，局部上电复位电路包括在各个功率岛中; 在另一类实施例中，取决于检测到的接口电压电平，上电复位电路被自动重新编程，以在两种情况下使用相同的电路进行功率有效检测。

公开(公告)号：US07818490B2

公开(公告)日：2010-10-19

申请号：US11250238

申请日：2005-10-13

申请人： Kevin M. Conley

发明人： Kevin M. Conley

IPC分类号： G06F9/24

CPC分类号： G11C16/102 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C16/105 ,  G11C2216/16

摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

公开(公告)号：US07816181B1

公开(公告)日：2010-10-19

申请号：US12494803

申请日：2009-06-30

申请人： Shrikar Bhagath ,  Hem Takiar

发明人： Shrikar Bhagath ,  Hem Takiar

IPC分类号： H01L23/29 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of under-filling semiconductor die in a die stack and a semiconductor device formed thereby are disclosed. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

摘要翻译： 公开了一种芯片堆叠中的半导体管芯的填充方法及由此形成的半导体器件。 一旦半导体管芯形成，它们可以被堆叠和互连。 互连可能在芯片堆叠中的半导体管芯之间留下小的空间。 该空间有利地使用气相沉积方法完全填充，其中涂层作为蒸汽沉积，该蒸汽流过管芯堆叠的所有表面，包括进入堆叠中的管芯之间的空间。 然后，蒸汽沉积在模具之间和周围的表面上并形成完全填充模具堆叠中的模具之间的空间的膜。 在气相沉积填充过程中使用的材料可以例如是聚对二甲苯聚合物族的成员，并且在实施方案中可以是聚对二甲苯-N。

公开(公告)号：US07814262B2

公开(公告)日：2010-10-12

申请号：US11250794

申请日：2005-10-13

申请人： Alan W. Sinclair

发明人： Alan W. Sinclair

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/12 ,  G06F13/38

CPC分类号： G06F12/0246 ,  G06F2212/401

摘要： A change in the amount of data to be stored that results from various encoding, compression, encryption or other data transformation algorithms, is handled by individually identifying distinct units of the transformed data and storing such units in physical succession within storage blocks of a memory system such as flash memory. The data being stored may come from a host system external to the memory system or from an application running on a processor within the memory system.

摘要翻译： 由各种编码，压缩，加密或其他数据变换算法产生的要存储的数据量的变化通过单独地识别经变换的数据的不同单元并将这些单元在物理上连续存储在存储器系统的存储块内来处理 如闪存。 存储的数据可以来自存储器系统外部的主机系统或来自在存储器系统内的处理器上运行的应用程序。

公开(公告)号：US07810235B2

公开(公告)日：2010-10-12

申请号：US11618292

申请日：2006-12-29

申请人： Steven Sprouse ,  Patricio Collantes ,  Dhaval Parikh

发明人： Steven Sprouse ,  Patricio Collantes ,  Dhaval Parikh

IPC分类号： H01R43/20

CPC分类号： H01R13/6485 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49222

摘要： A method is disclosed for making a connector for preventing electrostatic discharge during connection of a USB-type connector. The connector includes a grounding clip provided within a recess formed at least partially down into the surface of the second level of the base block. The grounding clip may have a proximal end affixed to a proximal end of a signal ground pin of the plurality of signal pins, though the grounding clip and signal ground pin may be coupled at other locations along their lengths. The connector including the grounding clip may be affixed to a semiconductor device. A portion of the grounding clip is provided at a height above the surface of the base block such that, when a shroud is slid around the connector, the shroud engages and remains in contact with the grounding clip. Accordingly, any electrostatic discharge built up in the shroud travels from the shroud, through the ESD grounding clip, to the signal ground pin where it is harmlessly dissipated.

摘要翻译： 公开了一种制造用于在连接USB型连接器期间防止静电放电的连接器的方法。 连接器包括设置在至少部分地下降到基座的第二级的表面内的凹部内的接地夹。 接地夹可以具有固定到多个信号引脚的信号接地引脚的近端的近端，尽管接地夹和信号接地引脚可以沿其长度在其它位置耦合。 包括接地夹的连接器可以固定到半导体器件。 接地夹的一部分设置在基座表面上方的高度处，使得当护罩围绕连接器滑动时，护罩接合并保持与接地夹接触。 因此，在护罩中建立的任何静电放电从护罩通过ESD接地夹移动到信号接地引脚，在那里它被无害地消散。

公开(公告)号：US20100257308A1

公开(公告)日：2010-10-07

申请号：US12487063

申请日：2009-06-18

申请人： Jonathan HSU ,  Shai TRAISTER

发明人： Jonathan HSU ,  Shai TRAISTER

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7202 ,  G06F2212/7203

摘要： A memory system includes a controller and a memory array that stores partial-page data and complete-page data in separate areas. Data received from a host is sent from a memory controller to an on-chip cache prior to determining whether the data is partial-page data or complete-page data. After a determination is made, the data is stored at an address in the corresponding area.

摘要翻译： 存储器系统包括控制器和存储部分页面数据和完整页面数据在独立区域中的存储器阵列。 在确定数据是部分页数据还是完整页数据之前，从主机接收的数据从存储器控制器发送到片上高速缓存。 确定后，数据存储在相应区域的地址上。