公开(公告)号：US09915969B2

公开(公告)日：2018-03-13

申请号：US14797286

申请日：2015-07-13

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Evgeni Ginzburg ,  Eran Glickman

IPC: G06F1/04 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F9/4825

Abstract: In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. The method also includes preventing reallocation of a timer identifier (ID) associated with the timer to another timer after the expiration of the timer and until receipt of the timer release confirmation message at the timer management component.

公开(公告)号：US20180059177A1

公开(公告)日：2018-03-01

申请号：US15252577

申请日：2016-08-31

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： John M. PIGOTT

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3012 ,  G01R31/31723 ,  G01R31/318533 ,  G01R31/318575 ,  G01R31/318577

Abstract: An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.

公开(公告)号：US20180058970A1

公开(公告)日：2018-03-01

申请号：US15246097

申请日：2016-08-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Philippe Garre ,  Silvia Garre ,  William DeWitt McWhorter ,  Larry Dale Metzler

IPC: G01L27/00 ,  G01L19/00

CPC classification number: G01L27/00 ,  G01L19/0092

Abstract: A test chamber is used within a system for testing microelectromechanical systems (MEMS) pressure sensors. The system includes a processor, two air tanks pressurized to different air pressures, a high speed switch mechanism, and the test chamber. The test chamber houses a MEMS pressure sensor to be tested, a control pressure sensor, and a temperature sensor. The MEMS pressure sensor and the control pressure sensor are located in a cavity within the test chamber. The cavity is of minimal size and has a domed inner surface. A response time of the MEMS pressure sensor within the cavity can be characterized by utilizing the system and subjecting the MEMS pressure sensor to a pressure stimulus pulse produced by switching between the two air tanks.

公开(公告)号：US20180046392A1

公开(公告)日：2018-02-15

申请号：US15236459

申请日：2016-08-14

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： VIVEK SINGH ,  AMAN DAHIYA ,  NAVDEEP SINGH GILL ,  PIYUSH K. UPADHYAY

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048

Abstract: A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. The data transaction is either a read transaction or a write transaction. The system includes an input and output interface in communication with the master for receiving a data transaction request, an identifying unit that identifies a type of the data transaction, a control unit that selectively enables at least one of the first and second cuts based on the data transaction type, and a data processing unit that processes data to be read from or written to the enabled cut based on the data transaction type.

公开(公告)号：US09893714B2

公开(公告)日：2018-02-13

申请号：US14841712

申请日：2015-09-01

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Akshat Mittal ,  Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh

IPC: G05D16/00 ,  H03H17/06 ,  H03H17/02

CPC classification number: H03H17/06 ,  H03H17/0225 ,  H03H17/0294

Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

公开(公告)号：US09891986B2

公开(公告)日：2018-02-13

申请号：US15006130

申请日：2016-01-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Nikhil Sharma ,  Rajesh Gupta ,  Vivek Sharma

IPC: G06F11/00 ,  G06F11/10 ,  G06F13/28 ,  G06F13/40 ,  G06F3/06 ,  G06F11/30

CPC classification number: G06F11/1016 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/068 ,  G06F11/3027 ,  G06F13/28 ,  G06F13/404 ,  G06F2201/81 ,  G06F2201/87

Abstract: A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. The protection code processing circuit generates and inserts a protection code into data to be written to the memory, and removes a protection code from data read from the memory. The system facilitates error checking without requiring modification of the channels (e.g., bus width) used to read and/or write data to memory.

公开(公告)号：US20180039589A1

公开(公告)日：2018-02-08

申请号：US15227834

申请日：2016-08-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： HEMANT NAUTIYAL ,  RAJAN KAPOOR ,  ARVIND KAUSHIK ,  PUNEET KHANDELWAL

IPC: G06F13/24 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/4286 ,  Y02D10/14 ,  Y02D10/151

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

公开(公告)号：US20180033472A1

公开(公告)日：2018-02-01

申请号：US15223213

申请日：2016-07-29

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： JIANAN YANG

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C7/14

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C17/12 ,  G11C17/14 ,  G11C17/18

Abstract: Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.

公开(公告)号：US20180024951A1

公开(公告)日：2018-01-25

申请号：US15213875

申请日：2016-07-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Graham Edmiston

IPC: G06F13/28 ,  G06F9/50 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0683 ,  G06F9/4881

Abstract: A heterogeneous multi-processor device having a first processor component arranged to issue a data access command request, a second processor component arranged to execute a set of threads, a task scheduling component arranged to schedule the execution of threads by the second processor component, and an internal memory component. In response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component.

公开(公告)号：US09871135B2

公开(公告)日：2018-01-16

申请号：US15171047

申请日：2016-06-02

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Xin Lin ,  Hongning Yang ,  Ronghua Zhu ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L21/265

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66681

Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.