公开(公告)号：US20200328272A1

公开(公告)日：2020-10-15

申请号：US16382718

申请日：2019-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar SINGH ,  Shiv Kumar MISHRA

IPC: H01L29/06 ,  H01L27/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

公开(公告)号：US10804398B2

公开(公告)日：2020-10-13

申请号：US16160701

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.

公开(公告)号：US10797138B2

公开(公告)日：2020-10-06

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10797046B1

公开(公告)日：2020-10-06

申请号：US16369788

申请日：2019-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L27/07 ,  H01L49/02 ,  H01L29/78 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.

公开(公告)号：US10796750B2

公开(公告)日：2020-10-06

申请号：US16031439

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4074 ,  G11C11/4076

Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

公开(公告)号：US10795430B1

公开(公告)日：2020-10-06

申请号：US16421730

申请日：2019-05-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Igor Arsovski ,  Kushal Kamal

IPC: G06F1/3296 ,  G06F30/00 ,  G05F3/20

Abstract: A semiconductor device is disclosed that includes, among other things, a computing device including a plurality of transistors, an activity monitor to determine an activity metric associated with the plurality of transistors, and a power controller to, responsive to the activity metric indicating a first activity level, set a power supply voltage for the plurality of transistors to a first value, and responsive to the activity metric indicating a second activity level less than the first activity level, set the power supply voltage to a second value greater than the first value and apply a first reverse back bias voltage to the plurality of transistors to increase a threshold voltage of the plurality of transistors.

公开(公告)号：US20200312775A1

公开(公告)日：2020-10-01

申请号：US16368836

申请日：2019-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： RINUS TEK PO LEE ,  FUAD AL-AMOODY ,  ASLI SIRMAN ,  JOSEPH KYALO KASSIM ,  HUI ZANG ,  BHARAT V. KRISHNAN

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.

公开(公告)号：US10790198B2

公开(公告)日：2020-09-29

申请号：US16058494

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fuad H. Al-Amoody ,  Yiheng Xu ,  Rishikesh Krishnan

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.

公开(公告)号：US10788877B1

公开(公告)日：2020-09-29

申请号：US16787520

申请日：2020-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian T. Ventrone ,  Lansing D. Pickup

IPC: G06F1/32 ,  H03K3/037 ,  H03K17/00 ,  G06F1/04

Abstract: Embodiments of the disclosure provide a low power multiplexer (MUX) circuit, including: a first data input coupled to an input of a first pass gate device; a second data input coupled to an input of a second pass gate device; a hold latch having an input coupled to a data output of the MUX circuit and an output coupled to an input of a supplemental pass gate device; and a pulse generator for generating a HOLD pulse signal, wherein the HOLD pulse signal is coupled to a control input of the supplemental pass gate device. The hold latch is configured to hold a previously valid output data signal of the MUX circuit until a valid input data signal is available at the first data input or the second data input.

公开(公告)号：US20200303261A1

公开(公告)日：2020-09-24

申请号：US16360183

申请日：2019-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Jiehui Shu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.