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    Sequential read mode static random access memory (SRAM)
    4.
    发明授权
    Sequential read mode static random access memory (SRAM) 有权

    公开(公告)号：US10796750B2

    公开(公告)日：2020-10-06

    申请号：US16031439

    申请日：2018-07-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

    IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4074 ,  G11C11/4076

    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

    Activity-aware supply voltage and bias voltage compensation
    5.
    发明授权
    Activity-aware supply voltage and bias voltage compensation 有权

    公开(公告)号：US10795430B1

    公开(公告)日：2020-10-06

    申请号：US16421730

    申请日：2019-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Igor Arsovski ,  Kushal Kamal

    IPC: G06F1/3296 ,  G06F30/00 ,  G05F3/20

    Abstract: A semiconductor device is disclosed that includes, among other things, a computing device including a plurality of transistors, an activity monitor to determine an activity metric associated with the plurality of transistors, and a power controller to, responsive to the activity metric indicating a first activity level, set a power supply voltage for the plurality of transistors to a first value, and responsive to the activity metric indicating a second activity level less than the first activity level, set the power supply voltage to a second value greater than the first value and apply a first reverse back bias voltage to the plurality of transistors to increase a threshold voltage of the plurality of transistors.

    SEQUENTIAL READ MODE STATIC RANDOM ACCESS MEMORY (SRAM)
    6.
    发明申请
    SEQUENTIAL READ MODE STATIC RANDOM ACCESS MEMORY (SRAM) 审中-公开

    公开(公告)号：US20200020388A1

    公开(公告)日：2020-01-16

    申请号：US16031439

    申请日：2018-07-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

    IPC: G11C11/419 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4074

    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

    Transmission system having duplicate transmission systems for individualized precharge and output timing
    9.
    发明授权
    Transmission system having duplicate transmission systems for individualized precharge and output timing 有权

    公开(公告)号：US09893765B1

    公开(公告)日：2018-02-13

    申请号：US15464397

    申请日：2017-03-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Xiaoli Hu ,  Wei Zhao ,  Chao Meng ,  Xiaoxiao Li

    IPC: H04B3/54 ,  H04B1/52 ,  H04B1/04

    CPC classification number: H04B3/54 ,  H04B1/04 ,  H04B1/52

    Abstract: Devices include a primary transmission system, and first and second duplicate (dummy or non-transmitting) transmission systems. The primary transmission system includes a primary transmitter circuit receiving a data signal, a primary transmission line connected to the primary transmitter circuit, and a primary receiver circuit connected to the primary transmission line. The first duplicate transmission system is connected to the primary transmitter circuit, and supplies a transmission timing control signal to the primary transmitter circuit. The primary transmitter circuit stops transmitting (e.g., stops reducing the voltage of the primary transmission line) when the transmission timing control signal is received. The second duplicate transmission system is connected to the primary receiver circuit, and supplies an output timing control signal to the primary receiver circuit, and the primary receiver circuit outputs the data signal when the output timing control signal is received.

    Double bandwidth algorithmic memory array
    10.
    发明授权
    Double bandwidth algorithmic memory array 有权

    公开(公告)号：US09870163B2

    公开(公告)日：2018-01-16

    申请号：US15140016

    申请日：2016-04-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Eric D. Hunt-Schroeder ,  Mark W. Kuemerle

    IPC: G06F3/06

    CPC classification number: G06F11/108

    Abstract: The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

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