公开(公告)号：US20090224238A1

公开(公告)日：2009-09-10

申请号：US12289252

申请日：2008-10-23

Applicant: Sun-il Kim ,  Young-soo Park ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

Inventor： Sun-il Kim ,  Young-soo Park ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869

Abstract: A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.

Abstract translation: 根据示例实施例的晶体管可以包括沟道层，分别接触沟道层的端部的源极和漏极，与沟道层分离的栅电极，介于沟道层和栅电极之间的栅极绝缘层和/ 或形成在沟道层和栅极绝缘层之间的插入层。 插入层可以具有与沟道层不同的功函数。

公开(公告)号：US20090001432A1

公开(公告)日：2009-01-01

申请号：US12073102

申请日：2008-02-29

Applicant: Sun-il Kim ,  I-hun Song ,  Young-soo Park ,  Dong-hun Kang ,  Chang-jung Kim ,  Jae-chul Park

Inventor： Sun-il Kim ,  I-hun Song ,  Young-soo Park ,  Dong-hun Kang ,  Chang-jung Kim ,  Jae-chul Park

IPC: H01L29/78 ,  H01L23/48 ,  H01L21/44 ,  H01L21/3205

CPC classification number: H01L29/7869

Abstract: Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Abstract translation: 提供了一种用于薄膜晶体管的沟道层，薄膜晶体管及其形成方法。 用于薄膜晶体管的沟道层可以包括掺杂有过渡金属的IZO（氧化铟锌）。 薄膜晶体管可以包括栅电极和形成在衬底上的沟道层，形成在栅极和沟道层之间的栅极绝缘层，以及与沟道层的端部接触的源电极和漏电极。

公开(公告)号：US20080203387A1

公开(公告)日：2008-08-28

申请号：US12007038

申请日：2008-01-04

Applicant: Dong-hun Kang ,  Stefanovich Genrikh ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim

Inventor： Dong-hun Kang ,  Stefanovich Genrikh ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim

IPC: H01L29/221 ,  H01L21/441

CPC classification number: H01L29/7869

Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.

Abstract translation: 提供一种薄膜晶体管及其制造方法。 薄膜晶体管可以包括栅极; 一个通道层; 源极和漏极，源极和漏极由金属形成; 和金属氧化物层，金属氧化物层形成在沟道层与源极和漏极之间。 金属氧化物层可以在沟道层和源极和漏极之间具有逐渐变化的金属含量。

公开(公告)号：US07397099B2

公开(公告)日：2008-07-08

申请号：US11710475

申请日：2007-02-26

Applicant: Soon-won Hwang ,  I-hun Song ,  Geun-young Yeom ,  Seok-jae Chung

Inventor： Soon-won Hwang ,  I-hun Song ,  Geun-young Yeom ,  Seok-jae Chung

IPC: H01L29/82

CPC classification number: H01L43/12 ,  G11C11/16

Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.

Abstract translation: 提供一种制造其中形成MTJ电池中的接触而不形成接触孔的纳米尺寸的MTJ电池的方法。 形成MTJ单元的方法包括在基板上形成MTJ层，通过图案化MTJ层形成MTJ单元区域，在MTJ层上依次沉积绝缘层和掩模层，暴露MTJ单元区域的上表面 通过以相同的蚀刻速率蚀刻掩模层和绝缘层，并在绝缘层和MTJ层上沉积金属层。

公开(公告)号：US20080093595A1

公开(公告)日：2008-04-24

申请号：US11976008

申请日：2007-10-19

Applicant: I-hun Song ,  Young-soo Park ,  Dong-hun Kang ,  Chang-jung Kim ,  Hyuck Lim

Inventor： I-hun Song ,  Young-soo Park ,  Dong-hun Kang ,  Chang-jung Kim ,  Hyuck Lim

IPC: H01L29/24 ,  H01L21/34

CPC classification number: H01L27/0688 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/105 ,  H01L29/7869

Abstract: A thin film transistor used as a selection transistor for a three-dimensional stacking cross point memory and a method of manufacturing the thin film transistor are provided. The thin film transistor includes a substrate, a gate, a gate insulation layer, a channel, a source and a drain. The gate may be formed on a portion of the substrate. The gate insulation layer may be formed on the substrate and the gate. The channel includes ZnO and may be formed on the gate insulation layer over the gate. The source and the drain contact sides of the channel.

Abstract translation: 提供了用作三维堆叠交叉点存储器的选择晶体管的薄膜晶体管和制造薄膜晶体管的方法。 薄膜晶体管包括衬底，栅极，栅极绝缘层，沟道，源极和漏极。 栅极可以形成在衬底的一部分上。 栅极绝缘层可以形成在衬底和栅极上。 通道包括ZnO，并且可以形成在栅极上的栅极绝缘层上。 通道的源极和漏极接触侧。

公开(公告)号：US07345898B2

公开(公告)日：2008-03-18

申请号：US11154941

申请日：2005-06-17

Applicant: Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

Inventor： Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

IPC: G11C5/06

CPC classification number: G11C11/5621 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract translation: 提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。 互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。 第一和第二非易失性存储器被布置成使得其上表面相邻。

公开(公告)号：US20070272922A1

公开(公告)日：2007-11-29

申请号：US11702222

申请日：2007-02-05

Applicant: Chang-jung Kim ,  I-hun Song ,  Dong-hun Kang ,  Young-soo Park

Inventor： Chang-jung Kim ,  I-hun Song ,  Dong-hun Kang ,  Young-soo Park

IPC: H01L29/12 ,  H01L21/00

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/78606

Abstract: A zinc oxide (ZnO) thin film transistor (TFT) and method of forming the same are provided. The ZnO may include a ZnO semiconductor channel, a conductive ZnO gate forming an electric field around the ZnO semiconductor channel, an ZnO gate insulator interposed between the conductive ZnO gate and the ZnO semiconductor channel and an insulating ZnO passivation layer on the ZnO semiconductor channel, the conductive ZnO gate and the ZnO gate insulator to protect the ZnO semiconductor channel, the conductive ZnO gate, and the ZnO gate insulator. A thin film transistor (TFT) may be formed by forming a semiconductor channel, forming a conductive gate having an electric field around the semiconductor channel, forming a gate insulator between the conductive gate and the semiconductor channel, and forming an insulating passivation layer on the semiconductor channel, the conductive gate and the gate insulator.

Abstract translation: 提供了一种氧化锌（ZnO）薄膜晶体管（TFT）及其形成方法。 ZnO可以包括ZnO半导体沟道，在ZnO半导体沟道周围形成电场的导电ZnO栅极，介于导电ZnO栅极和ZnO半导体沟道之间的ZnO栅极绝缘体和ZnO半导体沟道上的绝缘ZnO钝化层， 导电ZnO栅极和ZnO栅极绝缘体，以保护ZnO半导体通道，导电ZnO栅极和ZnO栅极绝缘体。 可以通过形成半导体沟道来形成薄膜晶体管（TFT），在半导体沟道周围形成具有电场的导电栅极，在导电栅极和半导体沟道之间形成栅极绝缘体，并在其上形成绝缘钝化层 半导体通道，导电栅极和栅极绝缘体。

公开(公告)号：US20070164338A1

公开(公告)日：2007-07-19

申请号：US11710475

申请日：2007-02-26

Applicant: Soon-won Hwang ,  I-hun Song ,  Geun-young Yeom ,  Seok-jae Chung

Inventor： Soon-won Hwang ,  I-hun Song ,  Geun-young Yeom ,  Seok-jae Chung

IPC: H01L29/94

CPC classification number: H01L43/12 ,  G11C11/16

Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.

公开(公告)号：US20060257753A1

公开(公告)日：2006-11-16

申请号：US11356258

申请日：2006-02-17

Applicant: Won-joo Kim ,  I-hun Song ,  Suk-pil Kim ,  Seung-hyuk Chang ,  Won-Il Ryu ,  Hoon Kim

Inventor： Won-joo Kim ,  I-hun Song ,  Suk-pil Kim ,  Seung-hyuk Chang ,  Won-Il Ryu ,  Hoon Kim

IPC: G03C5/00 ,  G21K5/00 ,  G03F1/00

CPC classification number: G21K1/062 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G21K2201/067

Abstract: A photomask and method thereof. In an example method, a photomask may be manufactured by forming an oxide layer on a surface, patterning the oxide layer to form an oxide pattern, the oxide pattern including a plurality of oxide pattern bodies and a plurality of oxide windows, filling the plurality of oxide windows with an absorbent to form an absorbent pattern and reducing the plurality of oxide pattern bodies. An example photomask may include an oxide pattern-based absorbent pattern including a plurality of absorbent pattern bodies and a plurality of absorbent pattern windows.

Abstract translation: 光掩模及其方法。 在一个示例性方法中，可以通过在表面上形成氧化物层来形成光掩模，图案化氧化物层以形成氧化物图案，氧化物图案包括多个氧化物图案体和多个氧化物窗口， 具有吸收剂的氧化物窗口以形成吸收图案并且还原多个氧化物图案体。 示例性光掩模可以包括基于氧化物图案的吸收图案，其包括多个吸收图案体和多个吸收图案窗。

公开(公告)号：US07061034B2

公开(公告)日：2006-06-13

申请号：US10830119

申请日：2004-04-23

Applicant: Sang-jin Park ,  Tae-wan Kim ,  Jung-hyun Lee ,  Wan-jun Park ,  I-hun Song

Inventor： Sang-jin Park ,  Tae-wan Kim ,  Jung-hyun Lee ,  Wan-jun Park ,  I-hun Song

IPC: H01L31/062

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C11/16 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/228

Abstract: In a magnetic random access memory (MRAM) having a transistor and a magnetic tunneling junction (MTJ) layer in a unit cell, the MTJ layer includes a lower magnetic layer, an oxidation preventing layer, a tunneling oxide layer, and an upper magnetic layer, which are sequentially stacked. The tunneling oxide layer may be formed using an atomic layer deposition (ALD) method. At least the oxidation preventing layer may be formed using a method other than the ALD method.

Abstract translation: 在单元中具有晶体管和磁隧道结（MTJ）层的磁性随机存取存储器（MRAM）中，MTJ层包括下磁层，防氧化层，隧道氧化物层和上磁层 ，顺序堆叠。 隧道氧化物层可以使用原子层沉积（ALD）方法形成。 至少防氧化层可以使用除ALD法以外的方法形成。