公开(公告)号：US08108741B2

公开(公告)日：2012-01-31

申请号：US12219815

申请日：2008-07-29

Applicant: Byoung-Sul Kim ,  Joon-Hee Lee ,  Kwan-Yong Jin ,  Seung-Hee Lee

Inventor： Byoung-Sul Kim ,  Joon-Hee Lee ,  Kwan-Yong Jin ,  Seung-Hee Lee

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/28 ,  G11C29/40 ,  G11C2029/4002

Abstract: A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.

Abstract translation: 提供一种具有安装测试电路及其安装测试方法的半导体存储器件。 用于包括多个存储块的半导体存储器件的测试电路可以包括：比较单元，用于比较从多个存储块中选出的至少两个存储块的测试数据，判断所选择的存储器的测试数据 块相同，并输出通过信号或失败信号作为标志信号; 以及输出选择单元，用于选择所选择的存储器块中的任何一个作为输出存储器块，并且每当从比较单元产生故障信号时改变输出存储器块，从而将其形成为可以减少误差的数据输出路径 发生。

公开(公告)号：US20110169040A1

公开(公告)日：2011-07-14

申请号：US13073794

申请日：2011-03-28

Applicant: Won Cheol SEO ,  Joon Hee LEE ,  Jong Kyun YOU ,  Chang Youn KIM ,  Jin Cheul SHIN ,  Hwa Mok KIM ,  Jang Woo LEE ,  Yeo Jin YOON ,  Jong Kyu KIM

Inventor： Won Cheol SEO ,  Joon Hee LEE ,  Jong Kyun YOU ,  Chang Youn KIM ,  Jin Cheul SHIN ,  Hwa Mok KIM ,  Jang Woo LEE ,  Yeo Jin YOON ,  Jong Kyu KIM

IPC: H01L33/60

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L27/156 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/46 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00

Abstract: Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside.

Abstract translation: 公开了一种发光器件及其制造方法。 发光器件包括衬底。 多个发光单元设置在基板的顶部上以彼此间隔开。 每个发光单元包括第一上半导体层，有源层和第二下半导体层。 反射金属层位于基板和发光单元之间。 防止反射金属层暴露于外部。

公开(公告)号：US07973354B2

公开(公告)日：2011-07-05

申请号：US12133146

申请日：2008-06-04

Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract translation: 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

公开(公告)号：US07961639B2

公开(公告)日：2011-06-14

申请号：US11605307

申请日：2006-11-29

Applicant: Joon-hee Lee

Inventor： Joon-hee Lee

IPC: G01R31/08 ,  H04L12/413 ,  H04J3/16

CPC classification number: H04L12/2801 ,  H04L12/413

Abstract: A method and apparatus are provided for transmitting data more efficiently between stations in a power line communication (PLC) network while preventing a hidden node problem. The method of transmitting data includes: detecting a hidden node in a network; and transmitting at least one of a request to send (RTS) command and a clear to send command (CTS) to the network before transmitting the data, if a hidden node is detected and a transmitting station a data packet having a size which is larger than a predetermined size. Using the method, interference of data transmissions and a low data throughput caused by the hidden node problem should be prevented.

Abstract translation: 提供了一种用于在电力线通信（PLC）网络中的站之间更有效地传输数据同时防止隐藏节点问题的方法和装置。 传输数据的方法包括：检测网络中的隐藏节点; 以及在发送数据之前，向网络发送发送请求（RTS）命令和清除发送命令（CTS）中的至少一个，如果检测到隐藏节点，并且发送站具有尺寸较大的数据分组 比预定尺寸。 使用该方法，应该防止数据传输的干扰和隐藏节点问题引起的低数据吞吐量。

公开(公告)号：US07441167B2

公开(公告)日：2008-10-21

申请号：US11811551

申请日：2007-06-11

Applicant: Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

Inventor： Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/28 ,  G11C2029/2602

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

公开(公告)号：US07397093B2

公开(公告)日：2008-07-08

申请号：US11241458

申请日：2005-09-30

Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract translation: 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

公开(公告)号：US20080093678A1

公开(公告)日：2008-04-24

申请号：US11646164

申请日：2006-12-27

Applicant: Joon-Hee Lee ,  Su-In Baek

Inventor： Joon-Hee Lee ,  Su-In Baek

IPC: G11C11/34 ,  G11C16/04 ,  H01L29/76

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.

Abstract translation: NAND型非易失性存储器件及其形成方法。 良好的偏置线以相等的间隔基本上平行于其它布线布置。 电连接到阱偏压线的有源区域以相同的等间隔基本上平行于其它有源区域布置。 结果，可以保持图案中的连续性和可重复性，并且可以最小化或防止图案缺陷。

公开(公告)号：US07274317B2

公开(公告)日：2007-09-25

申请号：US11432341

申请日：2006-05-12

Applicant: Yun-seong Eo ,  Il-ku Nam ,  Sung-jae Jung ,  Kwy-ro Lee ,  Heung-bae Lee ,  Kyu-don Choi ,  Joon-hee Lee

Inventor： Yun-seong Eo ,  Il-ku Nam ,  Sung-jae Jung ,  Kwy-ro Lee ,  Heung-bae Lee ,  Kyu-don Choi ,  Joon-hee Lee

IPC: H03M1/00

CPC classification number: H04B1/30 ,  H04B2001/0491

Abstract: A transmitter having a vertical BJT, capable of reducing power consumption, carrier leakage of a local oscillator and an error vector magnitude (EVM), is disclosed. In the transmitter, vertical BJTs implemented by a standard triplex well CMOS process are used in a frequency up-mixer and a baseband analog circuit including a DAC, an LPF, a VGA and a PGA, thereby improving the overall performance of the transmitter.

Abstract translation: 公开了具有垂直BJT的能够降低功耗，本地振荡器的载波泄漏和误差矢量幅度（EVM）的发射机。 在发射机中，通过标准三重阱CMOS工艺实现的垂直BJT用于上升混频器和包括DAC，LPF，VGA和PGA的基带模拟电路，从而提高发射机的整体性能。

公开(公告)号：US20070181334A1

公开(公告)日：2007-08-09

申请号：US11703117

申请日：2007-02-05

Applicant: Joon-Hee Lee ,  Ki-Hong Park

Inventor： Joon-Hee Lee ,  Ki-Hong Park

IPC: H01B3/44

CPC classification number: H01B3/306 ,  H01B3/421

Abstract: Disclosed are an insulated electric wire with partial discharge resistance and a composition for manufacturing the same. The insulated electric wire with partial discharge resistance according to the present invention includes an insulating base resin constituting a basic material of an insulated electric wire; an inorganic insulator included at a content of 5 to 40 parts by weight on the basis of 100 parts by weight of the insulating base resin; and a rubbery modifier included at a content of 0.1 to 30 parts by weight on the basis of 100 parts by weight of the insulating base resin to improve flexibility of an insulated electric wire. The insulated electric wire with partial discharge resistance of the present invention may be useful to prevent occurrence of cracks caused by winding of an insulated electric wire since the insulated electric wire has a sufficient partial discharge resistance and also enhances sufficient physical properties such as flexibility, pliability, bendability, elongation, etc. to maintain an electrically insulating property intactly by dispersing a stress, applied from an external force, by means of a rubber component attached to an end thereof.

Abstract translation: 公开了一种具有部分放电电阻的绝缘电线及其制造用组合物。 根据本发明的具有耐放电电阻的绝缘电线包括构成绝缘电线的基本材料的绝缘基础树脂; 基于绝缘基础树脂100重量份含有5至40重量份的无机绝缘体; 和含有0.1-30重量份的橡胶状改性剂，以100重量份的绝缘基础树脂为基础，以提高绝缘电线的柔韧性。 本发明的具有耐放电电阻的绝缘电线可用于防止由于绝缘电线具有足够的局部放电电阻而引起的由绝缘电线缠绕引起的裂纹的发生，并且还增强了足够的物理性能，如柔韧性，柔韧性 ，弯曲性，伸长率等，通过分散由外力施加的应力，通过附着在其一端的橡胶部件来完整地保持电绝缘性。

公开(公告)号：US20060057963A1

公开(公告)日：2006-03-16

申请号：US11225060

申请日：2005-09-14

Applicant: Joon-hee Lee

Inventor： Joon-hee Lee

IPC: H04B7/00

CPC classification number: H04W60/04 ,  H04W8/12 ,  H04W8/26 ,  H04W84/22

Abstract: A wireless network device and a communication method using the wireless network device are provided to simplify an association process of the device moving over different wireless networks and to enhance mobility of the device. The wireless network device includes an allocater allocating a device identifier (ID) to a predetermined device, an information generator generating information on the allocated device ID, and a first controller generating a packet containing the generated device ID and transmitting the generated packet to another wireless network.

Abstract translation: 提供了一种使用无线网络设备的无线网络设备和通信方法，以简化在不同无线网络上移动的设备的关联过程并增强设备的移动性。 所述无线网络装置包括向所述预定装置分配装置标识符（ID）的分配器，生成关于所分配的装置ID的信息的信息生成部，以及生成包含所生成的装置ID的分组的第一控制器，将所生成的分组发送给另一无线 网络。