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    Compressor
    42.
    发明申请
    Compressor 有权
    压缩机

    公开(公告)号：US20090175746A1

    公开(公告)日：2009-07-09

    申请号：US12227135

    申请日：2006-12-29

    申请人： Kyoung-Jun Park ,  Ji-Young Bae ,  Jin-Kook Kim ,  Bum-Joon Kim ,  Hyuk Nam ,  Jong-Mok Lee ,  Jong-Hyuk Kim ,  Kyeong-Ho Kim

    发明人： Kyoung-Jun Park ,  Ji-Young Bae ,  Jin-Kook Kim ,  Bum-Joon Kim ,  Hyuk Nam ,  Jong-Mok Lee ,  Jong-Hyuk Kim ,  Kyeong-Ho Kim

    IPC分类号： F04B39/10 ,  F04B53/10 ,  F04B53/14

    CPC分类号： F04B39/1073 ,  F04B39/1066 ,  Y10T137/7838

    摘要： A compressor having a casing to which a gas suction pipe is connected; a driving motor provided in the casing; a cylinder; a valve supporting plate (210) covering the cylinder (300), the valve supporting plate (210) having a suction hole (212) for sucking gas into the cylinder (300) and two discharge holes (211) for discharging gas compressed in the cylinder (300); a piston (100) having two protrusions (101) at a pressure surface in correspondence to the two discharge holes (211) of the valve supporting plate (210), the protrusions (101) having different sized cross-sections, the piston being linearly reciprocal in the cylinder (300) by receiving a driving force of the driving motor; a suction valve coupled to the valve supporting plate (210) to open and close the suction hole (212); a discharge valve coupled to the valve supporting plate to open and close the two discharge holes (211).

    摘要翻译： 一种压缩机，具有连接有吸气管的外壳; 设置在所述壳体内的驱动马达; 圆筒 覆盖所述气缸（300）的阀支撑板（210），所述阀支撑板（210）具有用于将气体吸入所述气缸（300）的吸入孔（212）和用于排出压缩在所述气缸 气缸（300）; 活塞（100），其在与所述阀支撑板（210）的两个排出孔（211）对应的压力表面处具有两个突起（101），所述突起（101）具有不同尺寸的横截面，所述活塞线性 通过接受驱动电动机的驱动力在气缸（300）中往复运动; 联接到所述阀支撑板（210）以打开和关闭所述吸入孔（212）的吸入阀; 排出阀，其连接到所述阀支撑板以打开和关闭所述两个排出孔。

    Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter
    43.
    发明授权
    Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter 有权
    制造具有CMOS反相器的节点接触结构的半导体器件的方法

    公开(公告)号：US07387919B2

    公开(公告)日：2008-06-17

    申请号：US11281346

    申请日：2005-11-16

    申请人： Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

    发明人： Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/092

    摘要： In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.

    摘要翻译： 在一个实施例中，使用使用节点杂质区域作为种子层的选择性外延生长工艺，形成本征单晶半导体插塞以穿过下绝缘层，并且在下绝缘层上形成单晶体半导体本体图案，使用 本征单晶半导体插头作为种子层。 当嵌入的单晶半导体插件掺杂有与节点杂质区相同的导电类型的杂质时，防止外围杂质区域被反掺杂。 结果，可以实现需要单晶薄膜晶体管的高性能半导体器件以及具有欧姆接触的节点接触结构。

    Dual damascene structure and methods of forming the same
    44.
    发明授权
    Dual damascene structure and methods of forming the same 失效
    双镶嵌结构及其形成方法

    公开(公告)号：US07358126B2

    公开(公告)日：2008-04-15

    申请号：US11333110

    申请日：2006-01-17

    申请人： Jun Seo ,  Jong-Hyuk Kim ,  Jong-Heui Song ,  Yung-Jun Kim ,  Min-Chul Chae

    发明人： Jun Seo ,  Jong-Hyuk Kim ,  Jong-Heui Song ,  Yung-Jun Kim ,  Min-Chul Chae

    IPC分类号： H01L23/43 ,  H01L21/4763

    CPC分类号： H01L21/76876 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76895 ,  H01L29/66477 ,  Y10T428/24331

    摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

    摘要翻译： 公开了一种双镶嵌结构和形成双镶嵌结构的方法。 双镶嵌结构包括绝缘构件，单晶构件和填充构件。 绝缘构件具有双镶嵌形状的开口。 填充构件形成在开口的侧面上。 单晶构件接触填充构件。 单晶构件填充开口。 为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。 填充构件形成在开口的侧面上。 外延的初步单晶构件生长以填满开口。 由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

    Methods of fabricating semiconductor devices having thin film transistors
    46.
    发明授权
    Methods of fabricating semiconductor devices having thin film transistors 有权
    制造具有薄膜晶体管的半导体器件的方法

    公开(公告)号：US07312110B2

    公开(公告)日：2007-12-25

    申请号：US11098648

    申请日：2005-04-04

    申请人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

    发明人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

    摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

    摘要翻译： 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

    Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns
    47.
    发明申请
    Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns 有权
    形成具有与上和下单元栅极图案接触的着陆焊盘的SRAM单元的方法

    公开(公告)号：US20070042554A1

    公开(公告)日：2007-02-22

    申请号：US11589618

    申请日：2006-10-30

    申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    IPC分类号： H01L21/336

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

    摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和方法消除了由于具有垂直堆叠的上下栅极图案的SRAM单元的结构特性而产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

    Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same
    49.
    发明申请
    Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same 有权
    具有单晶薄膜晶体管的半导体集成电路器件及其制造方法

    公开(公告)号：US20060102959A1

    公开(公告)日：2006-05-18

    申请号：US11280045

    申请日：2005-11-15

    申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim ,  Kun-Ho Kwak ,  Hoon Lim

    发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim ,  Kun-Ho Kwak ,  Hoon Lim

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern. Subsequently, the sacrificial layer pattern is selectively removed to form a cavity in the capping layer, and a planarized single crystalline semiconductor body pattern is formed to fill the cavity and the opening.

    摘要翻译： 提供具有单晶薄膜晶体管的半导体集成电路器件及其制造方法。 半导体集成电路器件包括形成在半导体衬底上的层间绝缘层和贯穿层间绝缘层的单晶半导体插件。 在层间绝缘层上设置单晶体半导体图案。 单晶半导体主体图案具有升高的区域并与单晶半导体插头接触。 形成具有升高区域的单晶半导体主体图案的方法包括在层间绝缘层上形成覆盖单晶半导体插塞的牺牲层图案。 形成覆盖牺牲层图案和层间绝缘层的覆盖层，并且对覆盖层进行图案化以形成露出牺牲层图案的一部分的开口。 随后，选择性地去除牺牲层图案以在封盖层中形成空腔，并且形成平坦化的单晶半导体主体图案以填充空腔和开口。

    SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same
    50.
    发明申请
    SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same 有权
    具有与上下单元栅极图案接触的着陆焊盘的SRAM单元及其形成方法

    公开(公告)号：US20060097328A1

    公开(公告)日：2006-05-11

    申请号：US11268138

    申请日：2005-11-07

    申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    IPC分类号： H01L29/76

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

    摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和该方法消除了具有垂直堆叠的上和下栅极图案的SRAM单元的结构特性所产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。