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1.发明申请CONTACT STRUCTURES IN SUBSTRATE HAVING BONDED INTERFACE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, METHODS OF FABRICATING THE SAME 失效具有接合界面的基板中的接触结构，包括其的半导体器件，其制造方法公开(公告)号：US20110287590A1
公开(公告)日：2011-11-24
申请号：US13204385
申请日：2011-08-05
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk KIm , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk KIm , Young-Chul Jang
IPC分类号： H01L21/768
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译： 接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和 下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。
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2.发明授权Contact structures in substrate having bonded interface, semiconductor device including the same, methods of fabricating the same 失效具有接合界面的基板中的接触结构，包括该接合界面的半导体器件，其制造方法公开(公告)号：US08343812B2
公开(公告)日：2013-01-01
申请号：US13204385
申请日：2011-08-05
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
IPC分类号： H01L21/82
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译： 接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和 下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。
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3.发明申请Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same 审中-公开具有接合界面的基板中的接触结构，包括其的半导体器件，其制造方法公开(公告)号：US20100012980A1
公开(公告)日：2010-01-21
申请号：US12504989
申请日：2009-07-17
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
IPC分类号： H01L29/68 , H01L23/52 , H01L21/768
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译： 接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和 下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。
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4.发明授权NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same 有权具有三维排列的存储单元的NAND闪存器件及其制造方法公开(公告)号：US07602028B2
公开(公告)日：2009-10-13
申请号：US11653890
申请日：2007-01-17
申请人： Yang-Soo Son , Young-Seop Rah , Won-Seok Cho , Soon-Moon Jung , Jae-Hoon Jang , Young-Chul Jang
发明人： Yang-Soo Son , Young-Seop Rah , Won-Seok Cho , Soon-Moon Jung , Jae-Hoon Jang , Young-Chul Jang
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/76895 , H01L21/8221 , H01L23/481 , H01L23/485 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.
摘要翻译： NAND闪速存储器件包括下半导体层和位于下半导体层上的上半导体层，位于下半导体层中的第一漏区和第一源区，以及位于下半导体层中的第二漏区和第二源区 上半导体层。 第一栅极结构位于下半导体层上，第二栅极结构位于上半导体层上。 位线位于上半导体层上方，并且至少一位位线插头连接在位线和第一漏极区之间，其中至少一位位线插头延伸穿过位于上半导体层中的漏极通孔。
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5.发明申请NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same 有权具有三维排列的存储单元的NAND闪存器件及其制造方法公开(公告)号：US20080087932A1
公开(公告)日：2008-04-17
申请号：US11653890
申请日：2007-01-17
申请人： Yang-Soo Son , Young-Seop Rah , Won-Seok Cho , Soon-Moon Jung , Jae-Hoon Jang , Young-Chul Jang
发明人： Yang-Soo Son , Young-Seop Rah , Won-Seok Cho , Soon-Moon Jung , Jae-Hoon Jang , Young-Chul Jang
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/76895 , H01L21/8221 , H01L23/481 , H01L23/485 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.
摘要翻译： NAND闪速存储器件包括下半导体层和位于下半导体层上的上半导体层，位于下半导体层中的第一漏区和第一源区，以及位于下半导体层中的第二漏区和第二源区 上半导体层。 第一栅极结构位于下半导体层上，第二栅极结构位于上半导体层上。 位线位于上半导体层上方，并且至少一位位线插头连接在位线和第一漏极区之间，其中至少一位位线插头延伸穿过位于上半导体层中的漏极通孔。
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6.发明申请METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING METALLIZATION COMPRISING SELECT LINES, BIT LINES AND WORD LINES 有权形成包含选择线，位线和字线的金属化的半导体器件的方法公开(公告)号：US20120009767A1
公开(公告)日：2012-01-12
申请号：US13236000
申请日：2011-09-19
申请人： Young-Chul JANG , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
发明人： Young-Chul JANG , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
IPC分类号： H01L21/20
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。
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公开(公告)号：US20080067517A1
公开(公告)日：2008-03-20
申请号：US11655115
申请日：2007-01-19
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
IPC分类号： H01L29/772 , H01L21/8234
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。
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8.发明授权Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 有权用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法公开(公告)号：US08399308B2
公开(公告)日：2013-03-19
申请号：US13236000
申请日：2011-09-19
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
IPC分类号： H01L21/82
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。
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9.发明申请Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 失效用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法公开(公告)号：US20100035386A1
公开(公告)日：2010-02-11
申请号：US12588240
申请日：2009-10-08
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
IPC分类号： H01L21/768
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。
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10.发明授权Semiconductor memory device having metallization comprising select lines, bit lines and word lines 有权具有包括选择线，位线和字线的金属化的半导体存储器件公开(公告)号：US07601998B2
公开(公告)日：2009-10-13
申请号：US11655115
申请日：2007-01-19
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Yang-Soo Son , Min-Sung Song
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.
摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。
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