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111 条记录 (耗时 0.033 秒)

    Semiconductor device
    41.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07660085B2

    公开(公告)日：2010-02-09

    申请号：US11358226

    申请日：2006-02-22

    申请人： Hiroshi Furuta ,  Kenji Hibino ,  Hidetaka Natsume ,  Toshikatsu Jinbo ,  Kiyokazu Hashimoto

    发明人： Hiroshi Furuta ,  Kenji Hibino ,  Hidetaka Natsume ,  Toshikatsu Jinbo ,  Kiyokazu Hashimoto

    IPC分类号： H02H3/22

    CPC分类号： G11C5/14

    摘要： A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

    摘要翻译： 电源保护元件的常规布局不能充分地保护内部电路免受流入从厚主布线分支的窄支线的浪涌电流的影响。 根据本发明的实施例的半导体器件包括围绕端子连接的电源保护元件; 与VCC焊盘或GND焊盘连接的主要配线; 从主布线分支的分支线，向半导体器件的功能块施加电源电位或地电位; 分支部分，其分支线从主布线分支; 以及与分支线连接的内部电源保护元件。

    SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE
    43.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE 失效
    半导体器件和测试半导体器件的方法

    公开(公告)号：US20080192554A1

    公开(公告)日：2008-08-14

    申请号：US12018993

    申请日：2008-01-24

    申请人： Kiyokazu HASHIMOTO ,  Nobutoshi TSUNESADA

    发明人： Kiyokazu HASHIMOTO ,  Nobutoshi TSUNESADA

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/52 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/26 ,  G11C29/50004

    摘要： A semiconductor device includes: a first memory; and a second memory. The first memory includes: a first memory cell array configured to be divided into a plurality of sectors, an erasure time setting register configured to hold a sector erasure assurance time to assure an erasure time for erasing data stored in one sector, and a first control circuit configured to execute a sector erasure test in which data stored in at least one selected sector selected from the plurality of sectors are erased within the sector erasure assurance time. The second memory includes: a second memory cell array configured to have a data storage system different from that of the first memory cell array, and a second control circuit configured to execute a data hold test with respect to the second memory cell array while the sector erasure test is executed.

    摘要翻译： 半导体器件包括：第一存储器; 和第二个记忆。 第一存储器包括：第一存储单元阵列，被配置为被划分为多个扇区;擦除时间设置寄存器，被配置为保持扇区擦除保证时间，以确保用于擦除存储在一个扇区中的数据的擦除时间;以及第一控制 电路，被配置为执行扇区擦除测试，其中存储在从所述多个扇区中选择的至少一个所选扇区中的数据在所述扇区擦除保证时间内被擦除。 第二存储器包括：第二存储单元阵列，被配置为具有与第一存储单元阵列的数据存储系统不同的数据存储系统;以及第二控制电路，被配置为执行相对于第二存储单元阵列的数据保持测试， 执行擦除测试。

    Optical disc apparatus
    46.
    发明授权
    Optical disc apparatus 失效
    光盘装置

    公开(公告)号：US07177244B2

    公开(公告)日：2007-02-13

    申请号：US10567418

    申请日：2004-08-05

    申请人： Kiyokazu Hashimoto

    发明人： Kiyokazu Hashimoto

    IPC分类号： G11B7/00 ,  G11B5/09

    CPC分类号： G11B20/10009 ,  G11B7/0053 ,  G11B20/14 ,  G11B27/24 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2562

    摘要： There are provided a balance adjustment circuit (6) for adjusting levels of first and second detection signals from a tracking detector, a differential circuit (8) for generating a difference signal between the adjusted first and second detection signals, an AD conversion circuit (10) for digitizing the difference signal, a wobble signal detection circuit (14) for detecting a wobble signal from the digitized difference signal, an adder circuit (30) for generating a sum signal of the adjusted first and second detection signals, a binarization circuit (32) for converting the sum signal into a binarized signal, a latch circuit (33) for latching the binarized signal and converting the same into a timing signal, a control signal generation circuit (34) for generating a control signal based on the timing signal and the digitized difference signal, a residual component removal circuit (18) for removing a residual signal component included in the digitized difference signal based on the control signal and outputting a LPP detection signal, and an address detection circuit (21) for detecting address information from the LPP detection signal. The wobble signal and the LPP signal are detected reliably with a simple configuration.

    摘要翻译： 提供了一种用于调整来自跟踪检测器的第一和第二检测信号的电平的平衡调整电路（6），用于在经调整的第一和第二检测信号之间产生差分信号的差分电路（8），AD转换电路 ），用于从数字化差分信号中检测摆动信号的摆动信号检测电路（14），用于产生经调整的第一和第二检测信号的和信号的加法电路（30），二值化电路 32），用于将和信号转换为二值化信号;锁存电路（33），用于锁存二值化信号并将其转换为定时信号;控制信号生成电路（34），用于基于定时信号产生控制信号 和数字化差分信号，用于去除包括在数字化差分信号b中的残留信号分量的残余分量去除电路（18） 输出LPP检测信号，以及用于从LPP检测信号检测地址信息的地址检测电路（21）。 以简单的配置可靠地检测摆动信号和LPP信号。

    Playback clock extracting apparatus
    47.
    发明授权
    Playback clock extracting apparatus 失效
    播放时钟提取装置

    公开(公告)号：US6134064A

    公开(公告)日：2000-10-17

    申请号：US80385

    申请日：1998-05-18

    申请人： Masafumi Sato ,  Kiyokazu Hashimoto ,  Masato Izawa

    发明人： Masafumi Sato ,  Kiyokazu Hashimoto ,  Masato Izawa

    IPC分类号： G11B5/008 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  H03L7/091

    CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/1403 ,  H03L7/091 ,  G11B5/00813 ,  G11B5/09

    摘要： A playback clock extracting device having: a quantization member for quantizing, at a sampling clock rate having a rate twice a recording rate, a signal played back from a recording medium so as to output sample data, a digital equalizer for subjecting the sample data to digital equalization so as to alternately output playback data and PLL data at an interval of one sampling clock, cycle a ternary decision member for making a ternary decision as to whether the playback data is positive, zero or negative. The playback clock extracting device further having arithmetic unit for calculating a sampling phase error in the quantization member by multiplying a result of the decision of the ternary decision member by a difference between two successive data values of the PLL data outputted immediately prior to and immediately after the playback data for the decision of the ternary decision member, respectively, a sampling clock generating member which controls a phase and an oscillation frequency on the basis of the sampling phase error outputted by the arithmetic unit so as to generate the sampling clock, and a playback clock generating member which divides a frequency of the sampling clock by two so as to generate a playback clock for detecting the playback data.

    摘要翻译： 一种重放时钟提取装置，具有：量化部件，用于以具有两倍于记录速率的速率的采样时钟速率对从记录介质播放的信号进行量化，以输出采样数据;数字均衡器，用于使样本数据 数字均衡，以便以一个采样时钟的间隔交替地输出重放数据和PLL数据，循环一个三进制决策构件，用于作出关于重放数据是正的还是负的否定的三元决定。 重放时钟提取装置还具有运算单元，用于通过将三进制判定构件的判定结果乘以在紧接在之前和之后输出的PLL数据的两个连续数据值之间的差来计算量化构件中的采样相位误差 分别用于三进制判定器的判定的重放数据，采样时钟产生部件，其基于由运算器输出的采样相位误差来控制相位和振荡频率，以产生采样时钟;以及 将采样时钟的频率除以2的再现时钟产生部件，以便产生用于检测重放数据的重放时钟。

    Semiconductor memory device having a small memory cell driving circuit
    48.
    发明授权
    Semiconductor memory device having a small memory cell driving circuit 失效
    具有小存储单元驱动电路的半导体存储器件

    公开(公告)号：US6125074A

    公开(公告)日：2000-09-26

    申请号：US855889

    申请日：1997-05-12

    申请人： Nobuo Murakami ,  Kiyokazu Hashimoto

    发明人： Nobuo Murakami ,  Kiyokazu Hashimoto

    IPC分类号： G11C11/413 ,  G11C8/08 ,  G11C11/407 ,  G11C16/06 ,  G11C17/18 ,  G11C8/10

    CPC分类号： G11C8/08

    摘要： In a semiconductor memory device including memory cells, first and second decoders generate first and second selection signals, and a driver circuit generates a drive signal for driving the memory cells. The driver circuit includes a transfer gate, controlled by the first selection signal, thus passing the second selection signal to generate the drive signal.

    摘要翻译： 在包括存储单元的半导体存储器件中，第一和第二解码器产生第一和第二选择信号，驱动电路产生用于驱动存储单元的驱动信号。 驱动器电路包括由第一选择信号控制的传输门，从而传递第二选择信号以产生驱动信号。

    Semiconductor memory
    49.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5889716A

    公开(公告)日：1999-03-30

    申请号：US16274

    申请日：1998-01-30

    申请人： Kiyokazu Hashimoto

    发明人： Kiyokazu Hashimoto

    IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/06 ,  G11C7/02 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C16/32 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C7/06

    摘要： In a semiconductor memory storing multivalue information, a sense section includes a first latch receiving an output of a first differential amplifier in a sense amplifier, a second latch receiving an output of a second differential amplifier in the sense amplifier and an output of the first latch, and a third latch receiving an output of a third differential amplifier in the sense amplifier and an output of the second latch. When a selected memory cell has the lowest threshold, the output of the first latch becomes a low level, and correspondingly, the output of the second latch is forcibly brought to the low level in response to the low level of the output of the first latch, and then, the output of the third latch is forcibly brought to the low level in response to the low level of the output of the second latch. Therefore, even if the output of the second and third differential amplifiers varies because of power supply voltage noises, the data can be correctly read out without being influenced by the power supply voltage noises.

    摘要翻译： 在存储多值信息的半导体存储器中，感测部分包括接收读出放大器中的第一差分放大器的输出的第一锁存器，接收读出放大器中的第二差分放大器的输出的第二锁存器和第一锁存器的输出 以及第三锁存器，其接收读出放大器中的第三差分放大器的输出和第二锁存器的输出。 当所选择的存储单元具有最低阈值时，第一锁存器的输出变为低电平，并且相应地，响应于第一锁存器的输出的低电平，第二锁存器的输出被强制地变为低电平 然后，响应于第二锁存器的输出的低电平，第三锁存器的输出被强制地变为低电平。 因此，即使由于电源电压噪声而导致第二和第三差分放大器的输出变化，所以可以在不受电源电压噪声影响的情况下正确读出数据。

    Non-volatile semiconductor memory device equipped with high-speed sense amplifier unit
    50.
    发明授权
    Non-volatile semiconductor memory device equipped with high-speed sense amplifier unit 失效
    配有高速读出放大器单元的非易失性半导体存储器件

    公开(公告)号：US5293333A

    公开(公告)日：1994-03-08

    申请号：US744216

    申请日：1991-10-09

    申请人： Kiyokazu Hashimoto

    发明人： Kiyokazu Hashimoto

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/26 ,  G11C11/40

    CPC分类号： G11C16/26

    摘要： An electrically erasable and programmable read only memory device has a sense amplifier circuit for changing an output voltage level at the output node thereof indicative of either an erased or a write-in state of a memory cell to be accessed, and the output voltage level is compared with a reference voltage level so as to see whether the output voltage is indicative of the erased state or the write-in state, wherein the sense amplifier circuit is associated with a current make-up circuit for compensating the current to the output node of the sense amplifier circuit so that the output voltage level rapidly reaches a high or low voltage level regardless of fluctuation of the reference voltage level.

    摘要翻译： 电可擦除可编程只读存储器件具有用于改变其输出节点处的输出电压电平的读出放大器电路，其指示要访问的存储器单元的擦除状态或写入状态，并且输出电压电平为 与参考电压电平相比，以便看出输出电压是指示擦除状态还是写入状态，其中读出放大器电路与用于补偿到输出节点的电流的电流补偿电路相关联 读出放大器电路，使得无论参考电压电平的波动如何，输出电压电平快速达到高或低电压电平。