公开(公告)号：US06998686B2

公开(公告)日：2006-02-14

申请号：US10230944

申请日：2002-08-28

Applicant: Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

Inventor： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

Abstract translation: 描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。 栅电极结构具有三层金属栅电极和多晶硅层。 第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。 第二金属层用于设定栅电极结构的功函数。 第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

公开(公告)号：US20060017098A1

公开(公告)日：2006-01-26

申请号：US10896124

申请日：2004-07-20

Applicant: Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Justin Brask ,  Suman Datta ,  Robert Chau

Inventor： Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Justin Brask ,  Suman Datta ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L21/28194 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.

公开(公告)号：US20060000489A1

公开(公告)日：2006-01-05

申请号：US11217008

申请日：2005-08-30

Applicant: Michael Chan ,  Robert Bristol ,  Mark Doczy

Inventor： Michael Chan ,  Robert Bristol ,  Mark Doczy

IPC: B08B6/00

CPC classification number: G21K1/06 ,  B08B7/0057 ,  G03F7/70925 ,  Y10S134/902

Abstract: A method for cleaning optics in a chamber. The method can include introducing a first etchant into a chamber that encloses an optical component and a source of electromagnetic radiation that is suitable for lithography, ionizing the first etchant, and removing debris from a surface of the optical component.

Abstract translation: 一种清洁室内光学元件的方法。 该方法可以包括将第一蚀刻剂引入到包围光学部件的室中，以及适于光刻的电磁辐射源，电离第一蚀刻剂，以及从光学部件的表面去除碎屑。

公开(公告)号：US20050285213A1

公开(公告)日：2005-12-29

申请号：US10877836

申请日：2004-06-24

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/26586 ,  H01L21/28238 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可暴露于硅离子注入的垂直部分。 作为注入的结果，可以减小垂直部分的介电常数，减少边缘电容。

公开(公告)号：US20050263483A1

公开(公告)日：2005-12-01

申请号：US11196034

申请日：2005-08-03

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

IPC: B44C1/22 ,  C09K13/00 ,  C09K13/06 ,  H01L21/302 ,  H01L21/3213

CPC classification number: H01L21/32134 ,  C09K13/06

Abstract: Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.

Abstract translation: 半导体集成电路结构，例如包含金属层的堆叠，可以用修改的粘度蚀刻剂进行蚀刻。 例如，当蚀刻金属膜时，增加的粘度蚀刻剂可以减少底切。

公开(公告)号：US06968850B2

公开(公告)日：2005-11-29

申请号：US10197628

申请日：2002-07-15

Applicant: Michael Chan ,  Robert Bristol ,  Mark Doczy

Inventor： Michael Chan ,  Robert Bristol ,  Mark Doczy

IPC: B08B7/00 ,  G03F7/20

CPC classification number: G21K1/06 ,  B08B7/0057 ,  G03F7/70925 ,  Y10S134/902

Abstract: A method and system for cleaning collector optics in a light source chamber. In producing, for example, extreme ultraviolet light for lithography, debris such as tungsten can accumulate on optical components near a light source in the light source chamber.An etchant, such as a fluorine-containing gas, can be introduced into the light source chamber. The etchant is ionized via electrodes to generate free fluorine. The electrodes can be, for example, existing light source chamber components including the optical components. The fluorine can then react with the debris, forming gaseous compounds, which are pumped out of the light source chamber.

Abstract translation: 一种用于清洁光源室中的收集器光学元件的方法和系统。 例如，在制造用于光刻的极紫外光时，诸如钨的碎屑可以积聚在光源室中的光源附近的光学部件上。 诸如含氟气体的蚀刻剂可以被引入到光源室中。 蚀刻剂通过电极离子化以产生游离氟。 电极可以是例如包括光学部件的现有光源室部件。 然后，氟可以与碎屑反应，形成气体化合物，其被泵送出光源室。

公开(公告)号：US20050250258A1

公开(公告)日：2005-11-10

申请号：US10839077

申请日：2004-05-04

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L21/8238 ,  H01L21/335

CPC classification number: H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed second part of the high-k gate dielectric layer, the masking layer is removed. A second metal layer is then formed on the first metal layer and on the first part of the high-k gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，并在高k栅极电介质层的第一部分上形成掩模层。 在掩模层和高k栅极电介质层的暴露的第二部分上形成第一金属层之后，去除掩模层。 然后在第一金属层和高k栅极电介质层的第一部分上形成第二金属层。

公开(公告)号：US20050156171A1

公开(公告)日：2005-07-21

申请号：US11023881

申请日：2004-12-27

Applicant: Justin Brask ,  Brian Doyle ,  Mark Doczy ,  Robert Chau

Inventor： Justin Brask ,  Brian Doyle ,  Mark Doczy ,  Robert Chau

IPC: H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/49 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20050136677A1

公开(公告)日：2005-06-23

申请号：US10739173

申请日：2003-12-18

Applicant: Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/28185 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成至少约10埃厚的虚拟电介质层，并在虚拟电介质层上形成牺牲层。 在除去牺牲层和虚设电介质层以产生位于第一和第二间隔物之间​​的沟槽之后，在沟槽的底部的衬底上形成栅介质层，并且在栅介质层上形成金属层 。

公开(公告)号：US20050048791A1

公开(公告)日：2005-03-03

申请号：US10652546

申请日：2003-08-28

Applicant: Justin Brask ,  Uday Shah ,  Mark Doczy ,  Jack Kavalieros ,  Robert Chau ,  Robert Turkot ,  Matthew Metz

Inventor： Justin Brask ,  Uday Shah ,  Mark Doczy ,  Jack Kavalieros ,  Robert Chau ,  Robert Turkot ,  Matthew Metz

IPC: H01L21/336 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31111

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，以及修改高k栅极电介质层的第一部分，以确保其可被选择性地去除到高k栅极电介质层的第二部分。