公开(公告)号：US5808334A

公开(公告)日：1998-09-15

申请号：US340318

申请日：1994-11-14

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: G11C11/404 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: G11C7/18 ,  G11C11/4097

Abstract: In a semiconductor memory device having a memory cell array and sense amplifiers connected by bit lines, a conductive shield plate is arranged over the bit lines and between the memory cell array and the sense amplifiers.

Abstract translation: 在具有存储单元阵列和通过位线连接的读出放大器的半导体存储器件中，在位线之间以及存储单元阵列和读出放大器之间布置导电屏蔽板。

公开(公告)号：US5650647A

公开(公告)日：1997-07-22

申请号：US329056

申请日：1994-10-26

Applicant: Masao Taguchi ,  Taiji Ema

Inventor： Masao Taguchi ,  Taiji Ema

IPC: H01L21/02 ,  H01L29/68 ,  H01L29/78

CPC classification number: H01L28/87

Abstract: A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on an lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

Abstract translation: 动态随机存取存储器件包括具有形成存储电极的多个层叠导电膜的存储电容器。 在垂直相邻的导电膜之间形成间隙以包围存储电极。 在覆盖用于绝缘的栅电极的绝缘膜和存储电极的最下面的膜之间也形成间隙。 可以建立相邻膜之间的连接，使得最上面的膜垂直地延伸以与漏区接触。 此外，可以建立连接，使得上部膜直接安装在下部膜上。 膜的端部可以比其它部分厚。 层叠膜结构可以通过交替地形成由与覆盖栅电极的绝缘膜不同的材料制成的膜和导电膜来制造。

公开(公告)号：US5557221A

公开(公告)日：1996-09-17

申请号：US76434

申请日：1993-06-14

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H03K19/0185 ,  H03F3/45

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract translation: 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及根据该开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US5553032A

公开(公告)日：1996-09-03

申请号：US424212

申请日：1995-04-19

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051

Abstract: A dynamic random access memory includes a capacitor in at least one memory cell each for storing one bit digital data as a terminal voltage, at least one bit line corresponding to at least one memory cell, a gate provided for each of the capacitors in the memory cells and which controls an electrical connection/disconnection between a terminal of the capacitor in the memory cell which stores the terminal voltage and the bit line corresponding to the memory cell, and at least one data bus line provided for at least one bit line. A current is continuously supplied to each of at least one of the data bus lines from a predetermined source through a predetermined resistor, and a reading voltage output unit provided for each of the bit lines, connects a current input terminal thereof with a data bus corresponding to the bit line, and changes a voltage of the data bus according to the voltage change on the bit line.

Abstract translation: 动态随机存取存储器包括至少一个存储单元中的电容器，用于存储一位数字数据作为终端电压，至少一个与至少一个存储单元对应的位线，为存储器中的每个电容器提供的门 并且其控制存储端子电压的存储单元中的电容器的端子与对应于存储单元的位线之间的电连接/断开，以及至少一个用于至少一个位线的数据总线。 通过预定的电阻将电流连续提供给来自预定源的至少一条数据总线的电流，为每个位线提供读取电压输出单元，将其电流输入端与对应的数据总线相连 到位线，并根据位线上的电压变化改变数据总线的电压。

公开(公告)号：US5452649A

公开(公告)日：1995-09-26

申请号：US395111

申请日：1995-02-27

Applicant: Masao Taguchi ,  Yoshitaka Hirano ,  Koji Sengoku ,  Masayuki Nakatani ,  Mahito Orii ,  Akifumi Fujita

Inventor： Masao Taguchi ,  Yoshitaka Hirano ,  Koji Sengoku ,  Masayuki Nakatani ,  Mahito Orii ,  Akifumi Fujita

IPC: A23L3/04 ,  A23L3/00 ,  A23L3/02

CPC classification number: A23L3/001 ,  A23L3/02

Abstract: A food sterilizing apparatus has a simple configuration and can completely and efficiently sterilize food. The food sterilizing apparatus is designed to sterilize food contained in rigid food containers and comprises a food supplying section, a linear cylindrical heater, a linear cylindrical cooler and a discharge section, each having inlet and outlet ports arranged respectively at the upstream and downstream ends thereof, any two adjacent ones of said component sections being connected in parallel or rectangularly with each other at the respective outlet and inlet ports thereof with a sealing gate interposed therebetween, said component sections being further provided with respective pushers disposed at the upstream end thereof for moving rigid food containers downstream, each of said pushers having a stroke at least equal to the width of a rigid container.

Abstract translation: 食品消毒设备具有简单的结构，可以完全有效地消毒食物。 食品消毒装置设计用于对刚性食品容器中所含食物进行消毒，包括食物供应部分，直线圆柱形加热器，直线圆柱形冷却器和排放部分，每个具有分别位于其上游和下游端的入口和出口 所述组件部分中的任意两个相邻的部件在相应的出口和入口处彼此平行地或相互垂直连接，其间插有密封闸门，所述组件部分还设置有设置在其上游端的各个推动器，用于移动 每个所述推动器的行程至少等于刚性容器的宽度。

公开(公告)号：US5321659A

公开(公告)日：1994-06-14

申请号：US677702

申请日：1991-03-29

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/062

Abstract: A signal amplifier circuit suitable for a semiconductor memory device includes a first current mirror circuit for outputting a first current to a first signal line and for outputting a second mirror current, and a second current mirror circuit for outputting a third current to a second signal line and for outputting a fourth mirror current. The first and second signal line form a pair of complementary signal lines. The amplifier circuit also includes a third current mirror circuit for receiving the second and fourth mirror currents and for outputting an output signal based on a potential difference between the first and second data signal lines.

Abstract translation: 适用于半导体存储器件的信号放大器电路包括用于向第一信号线输出第一电流并输出第二反射镜电流的第一电流镜电路和用于将第三电流输出到第二信号线的第二电流镜电路 并输出第四反射镜电流。 第一和第二信号线形成一对互补信号线。 放大器电路还包括用于接收第二和第四镜电流的第三电流镜电路，并且用于基于第一和第二数据信号线之间的电位差来输出输出信号。

公开(公告)号：US5227675A

公开(公告)日：1993-07-13

申请号：US761548

申请日：1991-09-18

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07

CPC classification number: H02M3/07

Abstract: A semiconductor integrated circuit comprises a chip, an oscillator provided on the for producing an alternate current with a controlled amplitude that is determined by the drive voltage, a rectifier provided on the chip for receiving and converting the alternate current into a direct current, a voltage detector provided on the chip for detecting a voltage level of the direct current, and a controller provided on the chip and supplied with the detection signal from the voltage detector for controlling the oscillator such that the amplitude of the alternate current is changed in response to the detection signal. The controller increases the amplitude of the alternate current when the voltage level of the direct current has decreased below a predetermined level and decreases the amplitude of the alternate current when the voltage level of the direct current has increased above the predetermined level.

公开(公告)号：US5097303A

公开(公告)日：1992-03-17

申请号：US677560

申请日：1991-03-29

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: G05F1/56 ,  G05F1/46 ,  G11C5/14 ,  G11C11/403 ,  G11C11/407 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03K19/00

CPC classification number: G11C5/147 ,  G05F1/465

Abstract: An on-chip voltage regulator controls a gate of a regulator transistor having a first terminal connectable to receive an external power supply voltage and a second terminal connectable to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The regulator includes a clock receiving part for receiving a predetermined clock signal related to an operation of the internal circuit, and a regulator part for generating a gate voltage output to the gate of the regulator transistor on the basis of a state of the predetermined clock signal so that the regulator transistor can generate a substantially fixed internal voltage from the external power supply voltage irrespective of whether or not the internal circuit is operating.

公开(公告)号：US5001108A

公开(公告)日：1991-03-19

申请号：US207628

申请日：1988-06-16

Applicant: Masao Taguchi

Inventor： Masao Taguchi

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L39/06

CPC classification number: H01L23/53285 ,  H01L23/532 ,  H01L2924/0002

Abstract: Connecting a superconductive material wiring layer to an electrode formed of normal metals (i.e. non-superconductive metals, such as aluminum), and connecting a part of a semiconductor region to the normal metal. The normal metal can contact the superconductive wiring layer via a barrier metal, such as TiN, at least at a side wall of the superconductive wiring layer which is essentially orthogonal to the layer wiring. Accordingly, even when the wiring layer is anisotropically superconductive mainly in a direction parallel to the plane of deposition, the superconductive property can be fully realized. The inventive structure prevents copper atoms in the superconductive material and silicon atoms in the semiconductor region of the IC from producing an undesirable alloy. This improves reliability of the IC operation, i.e. the semiconductor material as well as the superconductive material is not deteriorated.

公开(公告)号：US4868418A

公开(公告)日：1989-09-19

申请号：US151757

申请日：1988-02-03

Applicant: Kenichi Imamura ,  Masao Taguchi

Inventor： Kenichi Imamura ,  Masao Taguchi

IPC: H03K5/08 ,  H01L29/68 ,  H03K5/02 ,  H03K5/24

CPC classification number: B82Y10/00 ,  H03K5/2418

Abstract: A comparator circuit comprises a differential amplifier supplied with a reference signal and an input signal. A resonant-tunneling transistor has a base supplied with an output signal of the differential amplifier. A collector is connected to a first power supply source via a resistor. An emitter is connected to a second power supply source. Therefore, it is possible to simplify a circuit configuration of the comparator circuit and to improve an operation speed of the comparator circuit by outputting an output signal from a connection portion between the resistor and the collector of the transistor.