中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.021 seconds)

    Structure for collection of ionization-induced excess minority carriers in a semiconductor substrate and method for the fabrication thereof
    41.
    发明授权
    Structure for collection of ionization-induced excess minority carriers in a semiconductor substrate and method for the fabrication thereof 失效
    用于在半导体衬底中收集电离诱导的过量少数载流子的结构及其制造方法

    公开(公告)号：US4424526A

    公开(公告)日：1984-01-03

    申请号：US268506

    申请日：1981-05-29

    Applicant: Robert H. Dennard ,  Matthew R. Wordeman

    Inventor： Robert H. Dennard ,  Matthew R. Wordeman

    IPC: H01L27/10 ,  H01L21/265 ,  H01L21/74 ,  H01L21/8242 ,  H01L23/556 ,  H01L27/108 ,  H01L29/78 ,  H01L31/00 ,  H01L27/02 ,  H01L29/80 ,  H01L29/92

    CPC classification number: H01L21/74 ,  H01L23/556 ,  H01L2924/0002

    Abstract: A semiconductor substrate which contains a buried grid-like region of enhanced concentration of an impurity type opposite to that of the semiconductor substrate; and method for the fabrication thereof which includes providing beneath the upper surface of a semiconductor substrate at a first depth a continuous region of a first impurity type which is the same as that of the semiconductor substrate and wherein at preselected isolated discontinuous locations beneath said surface the first impurity type is at a second depth beneath said surface which is greater than said first depth, and then providing beneath said first depth and substantially coincident with said second depth, a second impurity type opposite to that of the first type and at a dosage level lower than the dosage level of the first impurity type so as to provide a grid-like region of enhanced concentration of impurity type opposite to that of the semiconductor substrate for collecting excess minority carriers in the semiconductor substrate.

    Abstract translation: 一种半导体衬底，其包含与半导体衬底相反的杂质类型的增强浓度的埋入格栅状区域; 及其制造方法，其包括在第一深度处在半导体衬底的上表面下方提供与半导体衬底相同的第一杂质类型的连续区域，并且其中在所述表面下方的预选隔离不连续位置处， 第一杂质类型在所述表面下方的第二深度处，其大于所述第一深度，然后在所述第一深度之下提供与所述第二深度基本一致的第二杂质类型，与第一种类型相反的剂量级别 低于第一杂质类型的剂量水平，从而提供与用于收集半导体衬底中的过量少数载流子的与半导体衬底相反的增强浓度杂质类型的格栅状区域。

    Three-terminal cascade switch for controlling static power consumption in integrated circuits
    43.
    发明授权
    Three-terminal cascade switch for controlling static power consumption in integrated circuits 有权
    用于控制集成电路静态功耗的三端子级联开关

    公开(公告)号：US08586957B2

    公开(公告)日：2013-11-19

    申请号：US12551631

    申请日：2009-09-01

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L47/00

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.

    Abstract translation: 一种用于集成电路装置的三端开关装置，包括设置在第一端子和第二端子之间的相变材料（PCM）; 加热装置，其设置在所述第二端子和第三端子之间的直接电接触中，所述加热装置位于所述PCM附近，并且被配置为将所述PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态 ; 以及绝缘层，其被配置为将所述加热器与所述PCM材料电隔离，并且所述加热器从所述第一端子电隔离。

    CONFIGURATION OF CONNECTIONS IN A 3D STACK OF INTEGRATED CIRCUITS
    45.
    发明申请
    CONFIGURATION OF CONNECTIONS IN A 3D STACK OF INTEGRATED CIRCUITS 有权
    集成电路3D堆叠中的连接配置

    公开(公告)号：US20130049213A1

    公开(公告)日：2013-02-28

    申请号：US13217789

    申请日：2011-08-25

    Applicant: MICHAEL R. SCHEUERMANN ,  JOEL A. SILBERMAN ,  MATTHEW R. WORDEMAN

    Inventor： MICHAEL R. SCHEUERMANN ,  JOEL A. SILBERMAN ,  MATTHEW R. WORDEMAN

    IPC: H01L23/48 ,  H01L21/50

    CPC classification number: H01L23/522 ,  H01L22/32 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

    Abstract: There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.

    Abstract translation: 提供了具有两个或多个层的多层芯片堆叠的连接配置。 两个或更多个层中的每一个具有多个电路部件，即前侧和后侧。 连接配置包括具有作为前侧连接的构件和未连接到前侧连接的后侧连接的连接对。 前侧连接和后侧连接在两层或多层之间的给定层上彼此相对定位，并且分别连接到给定层上的多个电路组件中的不同电路组件。 前侧连接和背侧连接中的至少一个还连接到来自两个或更多个层中的给定层的相邻层上的多个电路部件中的特定一个。

    Three-terminal cascade switch for controlling static power consumption in integrated circuits
    46.
    发明授权
    Three-terminal cascade switch for controlling static power consumption in integrated circuits 有权
    用于控制集成电路静态功耗的三端子级联开关

    公开(公告)号：US08143609B2

    公开(公告)日：2012-03-27

    申请号：US12551643

    申请日：2009-09-01

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L47/00 ,  H01L29/04

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    Abstract translation: 开关电路包括连接在电压供给端子和逻辑子块之间的多个三端子PCM开关装置。 每个开关装置包括设置在第一端子和第二端子之间接触的PCM，加热装置，其设置成接触在第二端子和第三端子之间，加热装置位于PCM附近，并且被配置为切换 PCM的可变形部分在较低电阻状态和较高电阻状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    Three-terminal cascade switch for controlling static power consumption in integrated circuits
    48.
    发明授权
    Three-terminal cascade switch for controlling static power consumption in integrated circuits 失效
    用于控制集成电路静态功耗的三端子级联开关

    公开(公告)号：US07646006B2

    公开(公告)日：2010-01-12

    申请号：US11393259

    申请日：2006-03-30

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L47/00

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    Abstract translation: 配置成用于控制集成电路中的静态功耗的开关电路包括连接在电压源端子和集成电路逻辑的对应子块之间的多个三端子相变材料（PCM）开关器件。 每个PCM切换装置还包括设置在第一端子和第二端子之间接触的PCM，设置在第二端子和第三端子之间的加热装置，加热装置位于PCM附近，并且被配置为将 PCM的可变形部分的电导率在较低电阻结晶状态和较高电阻无定形状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    Differential and hierarchical sensing for memory circuits
    49.
    发明授权
    Differential and hierarchical sensing for memory circuits 有权
    存储电路的差分和分层感测

    公开(公告)号：US07564729B2

    公开(公告)日：2009-07-21

    申请号：US12057011

    申请日：2008-03-27

    Applicant: John Edward Barth, Jr. ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    Inventor： John Edward Barth, Jr. ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    IPC: G11C7/02

    CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

    Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

    Abstract translation: 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

Patent Agency Ranking