公开(公告)号：US10553643B2

公开(公告)日：2020-02-04

申请号：US16155083

申请日：2018-10-09

申请人： Microsemi SoC Corp.

发明人： John L McCollum

IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  H01L29/08 ,  H01L29/78

摘要： A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.

公开(公告)号：US10546633B2

公开(公告)日：2020-01-28

申请号：US15823323

申请日：2017-11-27

申请人： Microsemi SoC Corp.

发明人： John L McCollum

IPC分类号： G11C13/00

摘要： A resistive random access memory cell includes three resistive random access memory devices, each resistive random access memory device having an ion source layer and a solid electrolyte layer. The first and second resistive random access memory devices are connected in series such that either both ion source layers or both solid electrolyte layers are adjacent to one another. A third resistive random access memory device is connected in series with the first and second resistive random access memory devices.

公开(公告)号：US10523208B2

公开(公告)日：2019-12-31

申请号：US16177340

申请日：2018-10-31

申请人： Microsemi SoC Corp.

发明人： Volker Hecht ,  Jonathan W. Greene

IPC分类号： H03K19/177

摘要： A 4-input lookup table module including eight first-rank 2-input multiplexers, four second-rank multiplexers, two third-rank multiplexers, and one fourth-rank multiplexer, the first-rank through fourth-rank multiplexers forming a tree structure. A select input of the fourth-rank multiplexer is coupled to a first input node. Select inputs of the third-rank multiplexers are coupled to a second input node. Select inputs of a first and a second adjacent ones of the second rank 2-input multiplexers are electrically isolated from select inputs of a third and a fourth adjacent ones of the second rank 2-input multiplexers. Select inputs of a first through a fourth adjacent ones of the first rank 2-input multiplexers are electrically isolated from select inputs of a fifth through an eighth adjacent ones of the first rank 2-input multiplexers.

公开(公告)号：US10511245B2

公开(公告)日：2019-12-17

申请号：US16180751

申请日：2018-11-05

申请人： Microsemi SoC Corp.

发明人： Battu Prakash Reddy ,  Ashwin Murali

IPC分类号： H02P21/22 ,  H02P25/03

摘要： A method for controlling the drive current in a stepper motor includes measuring stepper motor current, computing a load angle of the stepper motor, calculating a torque ratio of the stepper motor, generating a reference current as a function of the torque ratio and a maximum current setting for the stepper motor, and setting the drive current of the stepper motor as a function of the reference current.

公开(公告)号：US20190237139A1

公开(公告)日：2019-08-01

申请号：US16249291

申请日：2019-01-16

申请人： Microsemi SoC Corp.

发明人： John L. McCollum ,  Jonathan W. Greene

IPC分类号： G11C14/00 ,  H01L27/112 ,  H01L27/24 ,  G11C13/00 ,  G11C17/16 ,  G11C17/18 ,  H01L45/00 ,  G06F11/10 ,  G11C29/52

摘要： A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.

公开(公告)号：US20190190522A1

公开(公告)日：2019-06-20

申请号：US16177244

申请日：2018-10-31

申请人： Microsemi SoC Corp.

发明人： Jonathan W. Greene ,  Fei Li

IPC分类号： H03K19/177 ,  G06F7/544

CPC分类号： H03K19/17728 ,  G06F7/544 ,  H03K19/17736

摘要： An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.

公开(公告)号：US10147485B2

公开(公告)日：2018-12-04

申请号：US15714562

申请日：2017-09-25

申请人： Microsemi SoC Corp.

发明人： Volker Hecht

IPC分类号： G11C11/00 ,  G11C13/00

摘要： A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.

公开(公告)号：US20180241398A1

公开(公告)日：2018-08-23

申请号：US15956692

申请日：2018-04-18

申请人： Microsemi SoC Corp.

发明人： Jonathan Greene ,  Frank Hawley ,  John McCollum

IPC分类号： H03K19/177 ,  H01L27/24 ,  H01L45/00

CPC分类号： H03K19/1776 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/142 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H03K19/17724 ,  Y10S438/90

摘要： A resistive random-access memory device formed on a semiconductor substrate includes an interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via presents a substantially planar top surface. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer form an aligned stack having edges extending beyond outer edges of the first via. A dielectric barrier layer including a second via is formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.

公开(公告)号：US20140078830A1

公开(公告)日：2014-03-20

申请号：US14013339

申请日：2013-08-29

申请人： Microsemi SoC Corp.

发明人： John McCollum

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/40607 ,  G11C16/0466 ,  G11C16/26

摘要： A method for performing auto-refresh of a SONOS memory in a field programmable gate array in a system, includes sensing an auto-refresh condition, selecting a memory segment that has not yet been refreshed, storing the contents of memory segment, erasing the memory cells in the memory segment, and reprogramming the memory cells in the memory segment, until all of the memory segments have been reprogrammed

摘要翻译： 一种用于在系统中的现场可编程门阵列中执行SONOS存储器的自动刷新的方法，包括感测自动刷新条件，选择尚未刷新的存储器段，存储存储器段的内容，擦除存储器 存储器段中的单元，并重新编程存储器段中的存储器单元，直到所有存储器段已被重新编程