公开(公告)号：US11769779B2

公开(公告)日：2023-09-26

申请号：US16725687

申请日：2019-12-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Shiyu Sun

IPC: H01L27/146 ,  H01L21/285 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/1463 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/28525 ,  H01L21/76224 ,  H01L21/76237 ,  H01L27/1464 ,  H01L27/1469 ,  H01L27/14612 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

Abstract: A method for forming a deep trench isolation structure for a CMOS image sensor includes providing a trench that extends from a first side toward a second side of a semiconductor substrate. The trench has an opening on the first side and a bottom and sides. A conformal layer of B-doped oxide is deposited on the bottom and sides of the trench and is less than half a width of the trench leaving a depthwise recess in the trench. A second material is deposited on the conformal layer of B-doped oxide in the trench filling the recess in the trench to the first side. The conformal layer of B-doped oxide is annealed driving boron from the conformal layer of B-doped oxide to the semiconductor substrate forming a B-doped region as a passivation layer juxtaposed next to the conformal layer of B-doped oxide having negative fixed charges.

公开(公告)号：US11750950B1

公开(公告)日：2023-09-05

申请号：US17804238

申请日：2022-05-26

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Ling Fu ,  Tiejun Dai ,  Zhe Gao

IPC: H04N25/75 ,  H01L27/146 ,  H04N25/77 ,  H04N25/531 ,  H04N25/532

CPC classification number: H04N25/75 ,  H01L27/14612 ,  H04N25/531 ,  H04N25/77

Abstract: A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

公开(公告)号：US20230268357A1

公开(公告)日：2023-08-24

申请号：US17680045

申请日：2022-02-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Chao Niu

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464

Abstract: Image sensors include a pixel array arranged about an array center, each pixel of the pixel array having a photodiode formed in a semiconductor substrate, and a central deep trench isolation structure disposed in the semiconductor substrate relative to a pixel center between the photodiode and an illuminated surface of the semiconductor substrate. If the pixel center is not coincident with the array center, then the central deep trench isolation structure is disposed at a CDTI shift distance away from the pixel center.

公开(公告)号：US20230267739A1

公开(公告)日：2023-08-24

申请号：US17675183

申请日：2022-02-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： SHIMIAO LI ,  RUIJIANG LUO ,  ZHONGYANG HUANG ,  GUANSONG LIU

IPC: G06V20/40 ,  G06V10/40 ,  G06V20/56

CPC classification number: G06V20/46 ,  G06V10/40 ,  G06V20/56

Abstract: An image processing method and a device configured to implement the same are disclosed. The method comprises: from an imaging device, obtaining image data that comprises temporally consecutive image frames; performing feature extraction on each of the obtained image frames; dynamically retaining extracted feature data of the obtained image frames in a feature accumulation database by regulating data retention in the feature accumulation database to a selective subset of the extracted feature data from the obtained image frames; performing Random Sample Consensus (RANSAC) operation on the selective subset of the extracted feature data from the feature accumulation database; and generating an estimation model from output of the RANSAC operation based on at least one of an extracted feature data of a current image frame or extracted feature data of one or more temporally preceding image frames of the obtained image frames.

公开(公告)号：US11736833B1

公开(公告)日：2023-08-22

申请号：US17849354

申请日：2022-06-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Woon Il Choi

IPC: H04N25/77 ,  H04N25/75 ,  H04N25/57 ,  H04N23/741

CPC classification number: H04N25/77 ,  H04N25/75 ,  H04N25/57

Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is configured to transfer the image charge from the photodiode to a floating diffusion. A reset transistor coupled between a reset voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) includes an insulating region disposed between a first metal electrode and a second metal electrode. The first metal electrode is coupled to a bias voltage source, the second metal electrode is selectively coupled to the floating diffusion, and excess image charge photogenerated by the photodiode during an idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion.

公开(公告)号：US11729526B1

公开(公告)日：2023-08-15

申请号：US17808899

申请日：2022-06-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Woon Il Choi

IPC: H04N25/59 ,  H04N25/75 ,  H04N25/709

CPC classification number: H04N25/59 ,  H04N25/709 ,  H04N25/75

Abstract: A pixel circuit includes a transfer transistor coupled between a photodiode and a floating diffusion. A lateral overflow integration capacitor (LOFIC) includes an insulating region disposed between a first metal electrode coupled to a bias voltage source, and a second metal electrode selectively coupled to the floating diffusion. A multifunction reset transistor includes a gate, a drain, a first source, and a second source. The drain, the first source, and the second source are coupled to each other in response to a multifunction reset control signal turning the multifunction reset transistor on. The drain, the first source, and the second source are decoupled from one another in response to the multifunction reset control signal turning the multifunction reset transistor off. The drain is coupled to a reset voltage source, the first source is coupled to the first metal electrode, and the second source is coupled to the second metal electrode.

公开(公告)号：US11722801B1

公开(公告)日：2023-08-08

申请号：US17659042

申请日：2022-04-13

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Zhenfu Tian ,  Tao Sun ,  Liang Zuo ,  Yu-Shen Yang ,  Satoshi Sakurai ,  Rui Wang

IPC: H04N25/75 ,  H04N25/772

CPC classification number: H04N25/75 ,  H04N25/772

Abstract: A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.

公开(公告)号：US20230247330A1

公开(公告)日：2023-08-03

申请号：US17592389

申请日：2022-02-03

Applicant: OmniVision Technologies, Inc.

Inventor： Selcuk SEN ,  Liang ZUO ,  Rui WANG ,  Xuelian LIU ,  Min QU ,  Hiroaki EBIHARA

IPC: H04N5/359 ,  H01L27/146 ,  H04N5/374

CPC classification number: H04N5/3594 ,  H01L27/14643 ,  H01L27/14609 ,  H04N5/374

Abstract: In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

公开(公告)号：US20230215890A1

公开(公告)日：2023-07-06

申请号：US17570006

申请日：2022-01-06

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol MUN ,  Duli MAO ,  Bill PHAN

IPC: H01L27/146 ,  H04N5/3745

CPC classification number: H01L27/1463 ,  H04N5/3745 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: A backside-illuminated image sensor includes arrayed photodiodes separated by isolation structures, and interlayer dielectric between first layer of metal interconnect and substrate. The image sensor has barrier metal walls in the interlayer dielectric between isolation structures and first layer interconnect, the barrier metal walls aligned with the isolation structures and disposed between the isolation structures and first layer interconnect. The barrier metal wall deflects light passing through photodiodes of the sensor that would otherwise be reflected by interconnect into different photodiodes. The sensor is formed by providing a partially fabricated semiconductor substrate with photodiodes and source-drain regions formed; forming gate electrodes on a frontside surface of the semiconductor substrate, depositing an etch-stop layer over the gate electrodes; depositing interlayer dielectric on the etch-stop layer; forming trenches extending to the etch-stop layer through the interlayer dielectric, the trenches being between photodiodes; and filling trenches with metal to form barrier metal walls.

公开(公告)号：US11695944B2

公开(公告)日：2023-07-04

申请号：US17469724

申请日：2021-09-08

Applicant: OmniVision Technologies, Inc.

Inventor： Hitoshi Watanabe

IPC: H04N19/164 ,  H04N11/02 ,  H04N19/30 ,  H04N19/46 ,  H04N19/176 ,  H04N19/513 ,  H04N19/70 ,  H04N19/139 ,  H04N19/146

CPC classification number: H04N19/30 ,  H04N19/139 ,  H04N19/146 ,  H04N19/176 ,  H04N19/46 ,  H04N19/513 ,  H04N19/70

Abstract: A video encoding method includes (i) determining a current bit rate of a communication channel between a destination device and a source device that stores an input video frame, and (ii) generating a current reconstructed frame and an encoded bitstream at least in part via inter-frame coding of a current input video frame of a sequence of input video frames using a previously-generated reconstructed frame generated at least in part via inter-frame coding of a previous input video frame. The current reconstructed frame is a compressed version of the current input video frame. When both (i) a subsequent bit rate, determined after said inter-frame coding, is less than a threshold and (ii) the current bit rate exceeds the threshold, the method includes: (a) generating a downscaled reconstructed frame at least in part by downscaling the current reconstructed frame; and (b) appending the encoded bitstream with a bit sequence representing the downscaled reconstructed frame.