公开(公告)号：US11799471B2

公开(公告)日：2023-10-24

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687 ,  H03K19/00

CPC classification number: H03K17/161 ,  H03K17/6871 ,  H03K19/0008

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US11798992B2

公开(公告)日：2023-10-24

申请号：US17208971

申请日：2021-03-22

Applicant: SOCIONEXT INC.

Inventor： Sergey Pidin

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/0847 ,  H01L27/1203 ,  H01L29/0669 ,  H10B10/12

Abstract: A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.

公开(公告)号：US11785377B2

公开(公告)日：2023-10-10

申请号：US17825728

申请日：2022-05-26

Applicant: Socionext Inc.

Inventor： Katsumi Kobayashi

IPC: H04R1/34 ,  G02B27/01 ,  H04R1/02 ,  B60K35/00

CPC classification number: H04R1/345 ,  G02B27/0149 ,  H04R1/025 ,  B60K35/00 ,  B60K2370/157 ,  B60K2370/1529 ,  H04R2499/13 ,  H04R2499/15

Abstract: A display apparatus includes a display, and an acoustic unit connected to a sound source to transmit sound, wherein the acoustic unit includes a first cavity extending from the sound source in a first direction in which the sound is emitted, and a second cavity extending in a second direction that is different from the first direction, the second cavity being connected with the first cavity.

公开(公告)号：US11784188B2

公开(公告)日：2023-10-10

申请号：US17838895

申请日：2022-06-13

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/78 ,  H01L2027/11812 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11892

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US20230299070A1

公开(公告)日：2023-09-21

申请号：US18323244

申请日：2023-05-24

Applicant: Socionext Inc.

Inventor： Kengo TAKAHASHI ,  Yuji TAKAHASHI

IPC: H01L27/02 ,  H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/10

Abstract: A designing method of a semiconductor integrated circuit device includes: arranging a plurality of macros within a circuit arrangement area of a semiconductor integrated circuit device in which a plurality of power switch circuits are to be arranged in accordance with a first rule; detecting a narrow area from a first area, a width of the narrow area being less than a first value, the first area being an area in which the macros are not arranged within the circuit arrangement area; arranging the power switch circuits in the detected narrow area in accordance with a second rule different from the first rule; and arranging the power switch circuits in an area other than the narrow area within the first area in accordance with the first rule.

公开(公告)号：US11764792B2

公开(公告)日：2023-09-19

申请号：US17837516

申请日：2022-06-10

Applicant: Socionext Inc.

Inventor： David Hany Gaied Mikhael ,  Bernd Hans Germann ,  Ricardo Doldan Lorenzo

IPC: H03L7/099 ,  H03L7/089

CPC classification number: H03L7/099 ,  H03L7/0891 ,  H03L2207/06

Abstract: Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

公开(公告)号：US20230263503A1

公开(公告)日：2023-08-24

申请号：US18310231

申请日：2023-05-01

Applicant: Socionext Inc.

Inventor： Naoto ADACHI

IPC: A61B8/00

CPC classification number: A61B8/4483 ,  A61B8/54 ,  A61B8/52

Abstract: An ultrasonic device includes: a plurality of oscillation elements to generate ultrasonic waves toward a subject, and generate voltages according to ultrasonic waves reflected by the subject; a data generator to generate a predetermined number of sets of time-series data, each of the sets indicating change in time in a plurality of voltages generated by a predetermined number of oscillation elements, among the voltages generated by the plurality of oscillation elements; a data accumulator to accumulate the sets of time-series data generated by the data generator; a selector to select time-series data from among those generated by the data generator or those accumulated in the data accumulator; a data processor to generate image data by processing a predetermined number of sets of the selected time-series data; and a controller to cause the data generator to stop generating time-series data while the selector selects the accumulated time-series data.

公开(公告)号：US20230261664A1

公开(公告)日：2023-08-17

申请号：US18301708

申请日：2023-04-17

Applicant: Socionext Inc.

Inventor： Kenta ARUGA ,  Takeshi TAKAYAMA ,  Shota HINO

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/462

Abstract: A sampling circuit includes: a first capacitor including a first terminal and a second terminal; a second capacitor including a third terminal and a fourth terminal; a first input node configured to receive a first input voltage that is one of a differential input voltage; a second input node configured to receive a second input voltage that is the other of the differential input voltage; a first switch circuit configured to be provided between the first input node and the first terminal; a second switch circuit configured to be provided between the second input node and the third terminal; a third switch circuit configured to be provided between the first terminal and the third terminal; and a fourth switch circuit configured to be provided between the second terminal and the fourth terminal.

公开(公告)号：US20230260987A1

公开(公告)日：2023-08-17

申请号：US18105477

申请日：2023-02-03

Applicant: Socionext Inc.

Inventor： Masayoshi KOJIMA

IPC: H01L27/02

CPC classification number: H01L27/0285 ,  H01L27/0292

Abstract: A semiconductor device includes: an ESD protection circuit including a first n-channel MOS transistor provided between a signal terminal and a ground wire; and a control circuit electrically connected to the signal terminal, wherein, while a signal of a high level is being supplied to the signal terminal, the control circuit outputs a first voltage dropped from a high-level voltage of the signal to a gate of the first n-channel MOS transistor, and in response to a surge due to ESD being input into the signal terminal, outputs a second voltage lower than the first voltage to the gate of the first n-channel MOS transistor.

公开(公告)号：US20230224666A1

公开(公告)日：2023-07-13

申请号：US18184209

申请日：2023-03-15

Applicant: SOCIONEXT INC.

Inventor： Shuji MIYASAKA ,  Kazutaka ABE ,  Yasunori NARUSE

IPC: H04S7/00 ,  H04R3/00

CPC classification number: H04S7/302 ,  H04R3/005 ,  H04R2430/21 ,  H04S2420/01

Abstract: An audio communication device includes: a sound position determiner that determines sound localization positions for N audio signals in a virtual space having first and second walls; N sound localizers each performing sound localization processing to localize sound in the sound localization position determined by the sound position determiner, and outputting localized sound signals; an adder that sums the N localized sound signals, and outputs a summed localized sound signal. Each sound localizer performs the processing using: a first head-related transfer function (HRTF) assuming that a sound wave emitted from the sound localization position of the sound localizer determined by the sound position determiner directly reaches each ear of a hearer virtually present at the hearer position; and a second HRTF assuming that the sound wave emitted from the sound localization position reaches each ear of the hearer after being reflected by closer one of the first and second walls.