公开(公告)号：US08299802B2

公开(公告)日：2012-10-30

申请号：US12263290

申请日：2008-10-31

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC: G01R31/02

CPC classification number: G01R31/3167

Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

Abstract translation: 提出了一种能够监视模拟模块内的模拟电压的集成电路。 集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。 模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。 集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

公开(公告)号：US20120251116A1

公开(公告)日：2012-10-04

申请号：US13360314

申请日：2012-01-27

Applicant: Peng Li ,  Sergey Shumarayev ,  Jon M. Long ,  Tien Duc Pham

Inventor： Peng Li ,  Sergey Shumarayev ,  Jon M. Long ,  Tien Duc Pham

IPC: H04J14/02 ,  H04B10/02 ,  H04B10/06

CPC classification number: H04J14/02 ,  G02B6/12 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H04B10/40

Abstract: Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.

Abstract translation: 提供了提供具有用于高速关闭设备通信的集成光电子接口的集成电路设备电路的系统。 光电子接口可并入集成电路器件中，释放集成电路器件的部分或全部电I / O引脚。 收发器I / O通道可以设置在可以在电和光收发器I / O通道之间切换的集成电路装置上。

公开(公告)号：US08184651B2

公开(公告)日：2012-05-22

申请号：US12100360

申请日：2008-04-09

Applicant: Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

Inventor： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

IPC: H04L12/56

CPC classification number: H04L49/30 ,  H04L49/352

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

Abstract translation: 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US08174294B1

公开(公告)日：2012-05-08

申请号：US12910177

申请日：2010-10-22

Applicant: Weiqi Ding ,  Yanjing Ke ,  Sergey Shumarayev

Inventor： Weiqi Ding ,  Yanjing Ke ,  Sergey Shumarayev

IPC: H03B1/00

CPC classification number: H04L25/0272

Abstract: A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.

Abstract translation: 缓冲电路包括电流源电路，耦合到电流源电路的第一和第二开关电路，耦合到第一开关电路的第一电阻器，耦合到第二开关电路的第二电阻器和耦合到第二开关电路的第三开关电路， 第一和第二电阻。 当缓冲电路被配置为以当前模式逻辑缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第一电压的节点。 当缓冲电路被配置为以H桥缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第二电压的节点。

公开(公告)号：US08120429B1

公开(公告)日：2012-02-21

申请号：US12787722

申请日：2010-05-26

Applicant: Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

Inventor： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC: H03L7/00 ,  H03K3/03

CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

Abstract translation: 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US08098724B2

公开(公告)日：2012-01-17

申请号：US12287009

申请日：2008-10-02

Applicant: Sergey Shumarayev ,  Wilson Wong

Inventor： Sergey Shumarayev ,  Wilson Wong

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L1/205 ,  H04L25/03019

Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

Abstract translation: 用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。 均衡器电路可以包括可控制的可变DC增益和可控可变的AC增益。 电路还可以包括眼睛高度和眼睛宽度监视器电路，用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号。 第一输出信号可用于控制均衡器电路的直流增益，并且第二输出信号可用于控制均衡器电路的AC增益。

公开(公告)号：US20110257953A1

公开(公告)日：2011-10-20

申请号：US12762848

申请日：2010-04-19

Applicant: Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

Inventor： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US20110235756A1

公开(公告)日：2011-09-29

申请号：US13151717

申请日：2011-06-02

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H04L27/06

CPC classification number: H04L25/45

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract translation: 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US20110188621A1

公开(公告)日：2011-08-04

申请号：US12700433

申请日：2010-02-04

Applicant: Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

Inventor： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC: H04L7/00

CPC classification number: H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract translation: 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。 这可以帮助IC支持采用自动速度协商的通信协议。

公开(公告)号：US07940814B2

公开(公告)日：2011-05-10

申请号：US12576507

申请日：2009-10-09

Applicant: Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

Inventor： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC: H04J3/04

CPC classification number: H04L5/14 ,  H03K19/17744 ,  H04L27/00

Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Abstract translation: 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。