公开(公告)号：US08836443B2

公开(公告)日：2014-09-16

申请号：US13617347

申请日：2012-09-14

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC分类号： H01L23/66 ,  H03B5/08 ,  H03C3/22 ,  H01F27/29 ,  H03B5/12 ,  H01F27/28 ,  H01F21/12

CPC分类号： H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

摘要翻译： 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US08406258B1

公开(公告)日：2013-03-26

申请号：US12752984

申请日：2010-04-01

申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

IPC分类号： H04J3/06

CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。

公开(公告)号：US08299802B2

公开(公告)日：2012-10-30

申请号：US12263290

申请日：2008-10-31

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC分类号： G01R31/02

CPC分类号： G01R31/3167

摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

摘要翻译： 提出了一种能够监视模拟模块内的模拟电压的集成电路。 集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。 模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。 集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

公开(公告)号：US08184651B2

公开(公告)日：2012-05-22

申请号：US12100360

申请日：2008-04-09

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

IPC分类号： H04L12/56

CPC分类号： H04L49/30 ,  H04L49/352

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US08120429B1

公开(公告)日：2012-02-21

申请号：US12787722

申请日：2010-05-26

申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L7/00 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US08098724B2

公开(公告)日：2012-01-17

申请号：US12287009

申请日：2008-10-02

申请人： Sergey Shumarayev ,  Wilson Wong

发明人： Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L1/205 ,  H04L25/03019

摘要： Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

摘要翻译： 用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。 均衡器电路可以包括可控制的可变DC增益和可控可变的AC增益。 电路还可以包括眼睛高度和眼睛宽度监视器电路，用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号。 第一输出信号可用于控制均衡器电路的直流增益，并且第二输出信号可用于控制均衡器电路的AC增益。

公开(公告)号：US20110235756A1

公开(公告)日：2011-09-29

申请号：US13151717

申请日：2011-06-02

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04L27/06

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07940814B2

公开(公告)日：2011-05-10

申请号：US12576507

申请日：2009-10-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04J3/04

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07903679B1

公开(公告)日：2011-03-08

申请号：US11622396

申请日：2007-01-11

申请人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04L12/56

CPC分类号： H03K19/17744

摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

摘要翻译： 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

公开(公告)号：US07834712B2

公开(公告)日：2010-11-16

申请号：US12277810

申请日：2008-11-25

申请人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

发明人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

IPC分类号： H03B5/00

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

摘要翻译： 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。 选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。