公开(公告)号：US20080308875A1

公开(公告)日：2008-12-18

申请号：US12132148

申请日：2008-06-03

Applicant: Yong-Kyu LEE ,  Jeong-Uk HAN ,  Hee-Seog JEON ,  Young-Ho KIM ,  Myung-Jo CHUN ,  Jung-Ho MOON

Inventor： Yong-Kyu LEE ,  Jeong-Uk HAN ,  Hee-Seog JEON ,  Young-Ho KIM ,  Myung-Jo CHUN ,  Jung-Ho MOON

IPC: H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

Abstract translation: 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子栅极结构和衬底内的离子阱结结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US20080093646A1

公开(公告)日：2008-04-24

申请号：US11602075

申请日：2006-11-20

Applicant: Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young Ho Kim ,  Myung-Jo Chun

Inventor： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young Ho Kim ,  Myung-Jo Chun

IPC: H01L29/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the channel region to at least partially overlap the drain region, and a spacer arranged at each of both side walls of the gate structure. A threshold voltage value of the offset region changes depending on a dielectric constant of the spacer.

Abstract translation: 一种非易失性存储器件包括：半导体衬底，其具有形成在沟道区两端的源极/漏极区;栅极结构，通过与源极区隔开预定的距离而形成偏移区，并且包括电荷累积区和控制 顺序地沉积在沟道区域中以与漏极区域至少部分重叠的栅极以及布置在栅极结构的两个侧壁中的每一个侧壁处的间隔物。 偏移区域的阈值电压值根据间隔物的介电常数而变化。

公开(公告)号：US20080080244A1

公开(公告)日：2008-04-03

申请号：US11818238

申请日：2007-06-13

Applicant: Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

Inventor： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C16/0433 ,  G11C8/10 ,  G11C16/08 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

Abstract: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

Abstract translation: 非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。 可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。 本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。 更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。 还讨论了相关方法和系统。

公开(公告)号：US20080035962A1

公开(公告)日：2008-02-14

申请号：US11833019

申请日：2007-08-02

Applicant: Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

Inventor： Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66651

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区，形成在凹陷区的内表面上的凹陷沟道，其形成在源区和漏区之间的半导体衬底上， 掺杂掺杂物的外延半导体膜。 半导体器件还包括形成在凹槽上的栅极绝缘膜，以及填充凹陷区并形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20080001204A1

公开(公告)日：2008-01-03

申请号：US11647711

申请日：2006-12-29

Applicant: Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han

Inventor： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC: H01L29/76

CPC classification number: H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device and a method for fabricating the non-volatile memory device. The non-volatile memory device includes a memory cell located in a first conductive region and has a memory transistor, a selection transistor and a high voltage switching device located in a second conductive region close to the first conductive region. The memory cell is controlled by the high voltage switching device. At least one of the high voltage switching device, the memory transistor, or the selection transistor has a recessed channel region.

Abstract translation: 一种非易失性存储器件和用于制造非易失性存储器件的方法。 非易失性存储器件包括位于第一导电区域中的存储单元，并且具有位于靠近第一导电区域的第二导电区域中的存储晶体管，选择晶体管和高压开关器件。 存储单元由高电压开关装置控制。 高压开关器件，存储晶体管或选择晶体管中的至少一个具有凹陷沟道区域。

公开(公告)号：US20070267684A1

公开(公告)日：2007-11-22

申请号：US11804329

申请日：2007-05-17

Applicant: Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

Inventor： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源极区。

公开(公告)号：US07297600B2

公开(公告)日：2007-11-20

申请号：US11020899

申请日：2004-12-23

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L21/336

CPC classification number: H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

公开(公告)号：US07005349B2

公开(公告)日：2006-02-28

申请号：US10781761

申请日：2004-02-20

Applicant: Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

Inventor： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

Abstract translation: 使用反向自对准工艺制造双ONO型SONOS存储器的方法，其中在栅极下形成ONO电介质层，并且使用反向自对准工艺物理地分离成两部分，而与光刻极限无关。 为了促进反向自对准，采用用于限定ONO介电层宽度的缓冲层和间隔物。 因此，可以适当地调整编程和擦除期间的捕获电荷的分散，从而改善SONOS的特性。 本发明防止在编程和擦除操作之后的时间内重新分配电荷。

公开(公告)号：US06589943B2

公开(公告)日：2003-07-08

申请号：US09852131

申请日：2001-05-09

Applicant: Youngro Byun ,  Yong-Kyu Lee

Inventor： Youngro Byun ,  Yong-Kyu Lee

IPC: A61K31727

CPC classification number: C08B37/0075 ,  A61K31/727 ,  A61K47/542 ,  A61K47/554 ,  C08B37/00 ,  Y10S977/773 ,  Y10S977/775 ,  Y10S977/905 ,  Y10S977/915

Abstract: Formulations for enhanced mucosal absorption of heparin are disclosed. In one embodiment, a powdered heparin composition is made by dissolving an amphiphilic heparin derivative including heparin covalently bonded to a hydrophobic agent in a water phase, dispersing the water phase in an organic phase such that an emulsion is formed, and drying the emulsion. In another embodiment, an amorphiphilic heparin derivative dispersed in an oil phase is made by dissolving the amphiphilic heparin derivative in water or a water/organic co-solvent, dispersing the water or co-solvent in the oil phase, and evaporating the water or co-solvent. In another embodiment, heparin-containing nanoparticles having surfactant molecules associated with a hydrophobic agent on the outside of the nanoparticles are made by dissolving the amphiphilic heparin derivative in an aqueous solvent, mixing the surfactant with the aqueous solvent, and disrupting nanoparticles of the amphiphilic heparin derivative. Compositions made according to these methods are also described.

Abstract translation: 公开了用于增强肝素粘膜吸收的制剂。 在一个实施方案中，通过将包含共价键合在疏水剂上的肝素的两亲性肝素衍生物溶解在水相中来制备粉状肝素组合物，将水相分散在有机相中，形成乳液，并干燥乳液。 在另一个实施方案中，通过将两亲肝素衍生物溶解在水或水/有机共溶剂中，将水或助溶剂分散在油相中并蒸发水或共混物来制备分散在油相中的非晶性肝素衍生物 -溶剂。 在另一个实施方案中，通过将两亲性肝素衍生物溶解在水性溶剂中，将表面活性剂与水性溶剂混合，并破坏两性肝素的纳米颗粒，制备具有与纳米颗粒外侧疏水剂相关的表面活性剂分子的含肝素的纳米颗粒 衍生物。 还描述了根据这些方法制备的组合物。

公开(公告)号：US06486508B1

公开(公告)日：2002-11-26

申请号：US09568147

申请日：2000-05-10

Applicant: Yong-Kyu Lee

Inventor： Yong-Kyu Lee

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324

Abstract: A non-volatile semiconductor memory device and the fabricating method thereof, wherein control gates respectively formed at the active areas of the resultant structure for getting a corresponding pair of split floating gates continuously overlapped and buried diffusion areas formed at the substrate of the periphery of the field insulating layer positioned between neighboring source areas to prevent the source areas from being electrically disconnected by the field insulating layer, even if the floating gate pattern and the control gate pattern are respectively made by separate processes, so that there will be no mismatching between the aforementioned two patterns, thereby leading to no tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines, the schematic characteristic of cells makes it possible to program and erase a byte, and one contact hole is not used at each bit line, the number of contact holes gets small, thereby making it possible to scale down cells.

Abstract translation: 一种非易失性半导体存储器件及其制造方法，其中分别形成在所得结构的有源区上的控制栅极，用于使对应的一对分离浮置栅极连续地重叠，并且掩埋形成在 位于相邻源极区域之间的场绝缘层，以防止源极区域被场绝缘层电断开，即使浮栅图案和控制栅极图案分别由单独的工艺制成，从而不会发生不匹配 上述两种图案，由此导致根据奇/偶数字线不存在显示存储单元的不同特性的趋势，单元的示意性特性使得可以对字节进行编程和擦除，并且每个不使用一个接触孔 位线，接触孔的数量变小，从而形成 可能缩小细胞。