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41.发明授权Thin film transistor having improved manufacturability and method for manufacturing a display panel containing same 失效具有改进的可制造性的薄膜晶体管和用于制造包含它的显示面板的方法公开(公告)号：US08642367B2
公开(公告)日：2014-02-04
申请号：US13042348
申请日：2011-03-07
Applicant: Yu-Gwang Jeong , Young-Wook Lee , Sang-Gab Kim , Woo-Geun Lee , Min-Seok Oh , Jang-Soo Kim , Kap-Soo Yoon , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Seung-Hwan Shim , Sung-Hoon Yang , Ki-Hun Jeong
Inventor： Yu-Gwang Jeong , Young-Wook Lee , Sang-Gab Kim , Woo-Geun Lee , Min-Seok Oh , Jang-Soo Kim , Kap-Soo Yoon , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Seung-Hwan Shim , Sung-Hoon Yang , Ki-Hun Jeong
IPC: H01L21/02
CPC classification number: H01L27/127 , H01L27/1214 , H01L27/1259 , H01L27/1288 , H01L29/66765
Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.
Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。
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公开(公告)号：US20130320347A1
公开(公告)日：2013-12-05
申请号：US13951543
申请日：2013-07-26
Applicant: Young-Wook Lee , Jang-Soo Kim
Inventor： Young-Wook Lee , Jang-Soo Kim
IPC: H01L27/12
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136286 , G02F1/1365 , G02F1/1368 , G02F2001/134372 , G02F2001/136222 , G02F2001/13629 , H01L27/1248
Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.
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公开(公告)号：US20130009157A1
公开(公告)日：2013-01-10
申请号：US13614182
申请日：2012-09-13
Applicant: Young-Wook Lee , Jang-Soo Kim
Inventor： Young-Wook Lee , Jang-Soo Kim
IPC: H01L27/088
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136286 , G02F1/1365 , G02F1/1368 , G02F2001/134372 , G02F2001/136222 , G02F2001/13629 , H01L27/1248
Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.
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公开(公告)号：US08331149B2
公开(公告)日：2012-12-11
申请号：US12781926
申请日：2010-05-18
Applicant: Won-Joon Choi , Moon-Sig Joo , Ki-Hong Lee , Beom-Yong Kim , Jun-Yeol Cho , Young-Wook Lee
Inventor： Won-Joon Choi , Moon-Sig Joo , Ki-Hong Lee , Beom-Yong Kim , Jun-Yeol Cho , Young-Wook Lee
IPC: G11C16/04
CPC classification number: G11C16/0466 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , H01L29/7926
Abstract: A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.
Abstract translation: 3D非易失性存储器件包括：多个沟道结构，包括多个沟道层和层间电介质层，其交替堆叠并沿第一方向延伸; 多个字线在至少基本上垂直于第一方向的第二方向上延伸; 多个行选择线分别连接到多个通道层，并沿第二方向延伸; 以及分别连接到所述多个通道结构并沿所述第一方向延伸的多个列选择线。
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45.发明授权公开(公告)号：US08279388B2
公开(公告)日：2012-10-02
申请号：US12499212
申请日：2009-07-08
Applicant: Young-Wook Lee , Jang-Soo Kim , Kang-Woo Kim , Youn-Hak Jeong
Inventor： Young-Wook Lee , Jang-Soo Kim , Kang-Woo Kim , Youn-Hak Jeong
IPC: G02F1/1343 , G02F1/1335
CPC classification number: G02F1/136286 , G02F1/136209 , G02F2001/136222 , G02F2001/13629
Abstract: A liquid crystal display includes a first substrate, a plurality of gate lines formed on the first substrate, a plurality of data lines intersecting the gate lines, a plurality of thin film transistors connected to the gate lines and the data lines, a plurality of color filters formed on the gate lines, the data lines, and the thin film transistors, a plurality of first electrodes made of a transparent conductor formed on the color filters, and electrically connected to the thin film transistors, a first passivation layer formed on the first electrodes, a second electrode formed on the first passivation layer, and including a plurality of branch electrodes, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate.
Abstract translation: 液晶显示器包括第一基板，形成在第一基板上的多个栅极线，与栅极线交叉的多个数据线，连接到栅极线和数据线的多个薄膜晶体管，多个颜色 形成在栅极线，数据线和薄膜晶体管上的滤波器，形成在滤色器上的透明导体制成的多个第一电极，并与薄膜晶体管电连接;第一钝化层，形成在第一 电极，形成在第一钝化层上的第二电极，并且包括多个分支电极，面对第一基板的第二基板和设置在第一基板和第二基板之间的液晶层。
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Patent Agency Ranking
公开(公告)号：US20120194414A1
公开(公告)日：2012-08-02
申请号：US13419228
申请日：2012-03-13
Applicant: Woo-Geun LEE , Shi-Yul Kim , Jae-Hyoung Youn , Young-Wook Lee
Inventor： Woo-Geun LEE , Shi-Yul Kim , Jae-Hyoung Youn , Young-Wook Lee
IPC: G09G3/36
CPC classification number: G02F1/136286 , G02F1/136209 , G02F2001/13606 , G02F2001/136218 , G02F2001/136222 , G02F2201/40
Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.
Abstract translation: 提供了一种液晶显示器，用于防止光泄漏，同时提高了开口率和减少了数据线的负载。 液晶显示器包括形成在绝缘基板上并且彼此分开的栅极线和存储电极线，与栅极线相交的第一数据线和第二数据线，由栅极线和第一栅极线限定的第一像素电极 数据线和由栅极线和第二数据线限定并与第一像素电极相邻的第二像素电极。 此外，包括第一像素电极和第二像素电极之间的阻挡电极，其中第一数据线的至少一部分设置在第一像素电极下方，并且阻挡电极的至少一部分设置在第二像素电极下方 并且除了第一条数据线之外。
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公开(公告)号：US20120193634A1
公开(公告)日：2012-08-02
申请号：US13444768
申请日：2012-04-11
Applicant: Young-Wook Lee , Hong-Suk Yoo , Jean-Ho Song , Jae-Hyoung Youn , Woo-Geun Lee , Ki-Won Kim , Jong-In Kim
Inventor： Young-Wook Lee , Hong-Suk Yoo , Jean-Ho Song , Jae-Hyoung Youn , Woo-Geun Lee , Ki-Won Kim , Jong-In Kim
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/66742 , H01L27/1225 , H01L27/124 , H01L27/1248
Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.
Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。
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公开(公告)号：US20120007088A1
公开(公告)日：2012-01-12
申请号：US13238788
申请日：2011-09-21
Applicant: Young-Wook Lee , Jang-Soo Kim
Inventor： Young-Wook Lee , Jang-Soo Kim
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136286 , G02F1/1365 , G02F1/1368 , G02F2001/134372 , G02F2001/136222 , G02F2001/13629 , H01L27/1248
Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.
Abstract translation: 薄膜晶体管阵列面板包括基板; 形成在所述基板上的多条栅极线; 与栅极线相交的多条数据线; 连接到栅极线和数据线的多个薄膜晶体管; 形成在栅极线，数据线和薄膜晶体管的上部的多个滤色器; 形成在滤色器上并且包括透明导体的公共电极; 钝化层，其形成在所述公共电极的上部; 以及形成在钝化层的上部并且连接到每个薄膜晶体管的漏电极的多个像素电极。
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公开(公告)号：US07923176B2
公开(公告)日：2011-04-12
申请号：US12035086
申请日：2008-02-21
Applicant: Chong-Chul Chai , Mee-Hye Jung , Woo-Geun Lee , Woo-Seok Jeon , Young-Wook Lee , Jung-In Park , Jun-Hyung Souk , Won-Kie Chang , Shi-Yul Kim
Inventor： Chong-Chul Chai , Mee-Hye Jung , Woo-Geun Lee , Woo-Seok Jeon , Young-Wook Lee , Jung-In Park , Jun-Hyung Souk , Won-Kie Chang , Shi-Yul Kim
Abstract: A mask includes a transparent substrate, a light-blocking layer and a halftone layer. The light-blocking layer includes a source electrode pattern portion including a first electrode portion, a second electrode portion and a third electrode portion, and a drain electrode pattern portion disposed between the second electrode portion and the third electrode portion. The halftone layer includes a halftone portion corresponding to a spaced-apart portion between the source electrode pattern portion and the drain electrode pattern portion, and a dummy halftone portion more protrusive than ends of the second electrode portion and the third electrode portion. Thus, a photoresist pattern corresponding to a channel portion of a thin film transistor (TFT) may be formed with a uniform thickness, to thereby prevent an excessive etching of the channel portion.
Abstract translation: 掩模包括透明基板，遮光层和半色调层。 遮光层包括包括第一电极部分，第二电极部分和第三电极部分的源电极图案部分和设置在第二电极部分和第三电极部分之间的漏电极图案部分。 半色调层包括对应于源电极图案部分和漏电极图案部分之间的间隔部分的半色调部分和比第二电极部分和第三电极部分的端部更突出的虚拟半色调部分。 因此，可以形成对应于薄膜晶体管（TFT）的沟道部分的光致抗蚀剂图案，其厚度均匀，从而防止通道部分的过度蚀刻。
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公开(公告)号：US20110058418A1
公开(公告)日：2011-03-10
申请号：US12781926
申请日：2010-05-18
Applicant: Won-Joon CHOI , Moon-Sig Joo , Ki-Hong Lee , Beom-Yong Kim , Jun-Yeol Cho , Young-Wook Lee
Inventor： Won-Joon CHOI , Moon-Sig Joo , Ki-Hong Lee , Beom-Yong Kim , Jun-Yeol Cho , Young-Wook Lee
IPC: G11C16/04 , H01L29/66 , H01L21/336
CPC classification number: G11C16/0466 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , H01L29/7926
Abstract: A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.
Abstract translation: 3D非易失性存储器件包括：多个沟道结构，包括多个沟道层和层间电介质层，其交替堆叠并沿第一方向延伸; 多个字线在至少基本上垂直于第一方向的第二方向上延伸; 多个行选择线分别连接到多个通道层，并沿第二方向延伸; 以及分别连接到所述多个通道结构并沿所述第一方向延伸的多个列选择线。
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