公开(公告)号：US20180313673A1

公开(公告)日：2018-11-01

申请号：US16019087

申请日：2018-06-26

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/32 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US09619377B2

公开(公告)日：2017-04-11

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06 ,  G06F1/32

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US20150346001A1

公开(公告)日：2015-12-03

申请号：US14458885

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/32 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：US20140208135A1

公开(公告)日：2014-07-24

申请号：US13745731

申请日：2013-01-18

Applicant: APPLE INC.

Inventor： Shane J. Keil ,  Erik P. Machnicki ,  Josh P. de Cesare

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

Abstract translation: 公开了与集成电路内的电力管理有关的技术。 在一个实施例中，公开了一种包括电路和电源管理单元的装置。 功率管理单元被配置为基于可编程设置来提供是否允许对电路的尝试通信是使电路退出功率管理状态的指示。 在一些实施例中，该装置包括被配置成从设备将尝试的通信传送到电路的结构。 在这样的实施例中，电路被配置为响应于接收到尝试的通信而退出功率管理状态。 结构被配置为基于由电力管理单元提供的指示来确定是否发送尝试的通信。

公开(公告)号：US20230068494A1

公开(公告)日：2023-03-02

申请号：US17410657

申请日：2021-08-24

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

IPC: G06F3/06

Abstract: Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

公开(公告)号：US20210333132A1

公开(公告)日：2021-10-28

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US11079261B2

公开(公告)日：2021-08-03

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10777252B2

公开(公告)日：2020-09-15

申请号：US16109720

申请日：2018-08-22

Applicant: Apple Inc.

Inventor： Peter Fu ,  Gregory S. Mathews ,  Kai Lun Hsuing ,  Shane J. Keil

IPC: G06F13/00 ,  G11C11/406 ,  G06F13/16 ,  G06F13/10 ,  G06F13/12

Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

公开(公告)号：US20200149932A1

公开(公告)日：2020-05-14

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F1/3206 ,  G06F13/16

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US20200057579A1

公开(公告)日：2020-02-20

申请号：US16104307

申请日：2018-08-17

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.