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公开(公告)号：US20090173941A1
公开(公告)日：2009-07-09
申请号：US11970592
申请日：2008-01-08
IPC分类号： H01L29/04 , H01L21/205
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译： 制造具有设置在半导体结构的基板的表面上的非外延薄膜的半导体结构的方法; 并且公开了由其形成的半导体结构。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。
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42.发明申请RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 有权用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术公开(公告)号：US20080128712A1
公开(公告)日：2008-06-05
申请号：US12028191
申请日：2008-02-08
IPC分类号： H01L27/092 , H01L29/778
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译： 通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C） 用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积 具有足够高的替代碳含量的Si：C固有地是非选择性的。
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43.发明授权公开(公告)号：US06500772B2
公开(公告)日：2002-12-31
申请号：US09757072
申请日：2001-01-08
申请人： Ashima B. Chakravarti , Richard A. Conti , Chester Dziobkowski , Thomas Ivers , Paul Jamison , Frank Liucci
发明人： Ashima B. Chakravarti , Richard A. Conti , Chester Dziobkowski , Thomas Ivers , Paul Jamison , Frank Liucci
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C23C16/30 , H01L21/02167 , H01L21/02222 , H01L21/02274 , H01L21/0332 , H01L21/3145 , H01L21/31608 , H01L21/3185
摘要： A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.
摘要翻译： 一种在衬底上沉积膜的方法，包括在存在等离子体能量的情况下放置衬底，并使衬底与包含式（R-NH）4-nSiXn的化合物的反应性气体组分接触，其中R是烷基 基团，n为1,2或3，并且X选自氢或卤素。 反应性气体组合物还可以包含氧化剂和/或还原剂。
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公开(公告)号：US06436760B1
公开(公告)日：2002-08-20
申请号：US09838418
申请日：2001-04-19
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L21/32132
摘要： A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e.g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.
摘要翻译： 用于从多晶硅去除表面氧化物的方法包括在随后的多晶硅沉积步骤之前在多晶硅上沉积非常薄的锗层（例如，厚度为单层），然后在真空中加热锗覆盖的多晶硅以升华（除去）挥发性 氧化锗。 该方法适用于沟槽电容器的形成，其在电极形成中使用掺杂的非晶硅或掺杂的非晶SiGe材料。
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45.发明授权Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 有权用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升公开(公告)号：US07838932B2
公开(公告)日：2010-11-23
申请号：US12028191
申请日：2008-02-08
IPC分类号： H01L29/76257
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译： 通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C） 用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积 具有足够高的替代碳含量的Si：C固有地是非选择性的。
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46.发明授权Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 失效用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升公开(公告)号：US07473594B2
公开(公告)日：2009-01-06
申请号：US11459730
申请日：2006-07-25
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译： 通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C） 用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积 具有足够高的替代碳含量的Si：C固有地是非选择性的。
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公开(公告)号：US20080121926A1
公开(公告)日：2008-05-29
申请号：US11464664
申请日：2006-08-15
IPC分类号： H01L27/00
CPC分类号： H01L29/78 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L29/1054
摘要： An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.
摘要翻译： 集成电路系统包括衬底，衬底上的含碳的硅区域，衬底上的非含碳的硅区域和包含非含碳硅区域和碳 - 碳区域的硅 - 碳区域， 含硅区域。
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公开(公告)号：US06429149B1
公开(公告)日：2002-08-06
申请号：US09511394
申请日：2000-02-23
IPC分类号： H01L2131
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/02164 , H01L21/02337 , H01L21/31625
摘要： A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.
摘要翻译： 所公开的方法使用在衬底上的掺杂氧化物膜的低压化学气相沉积（LPCVD）。 该方法包括以下步骤：在LPCVD反应器中提供衬底并将BTBAS和氧气流入LPCVD反应器以在衬底上反应以在衬底上沉积氧化物膜。 掺杂的前体流入LPCVD反应器以在氧化膜沉积在衬底上时掺杂氧化膜。 该方法在相对低的LPCVD反应温度下产生掺杂的氧化物膜。
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49.发明授权Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill 失效掺有氟的硼磷硅玻璃用于低热量预算缺口填充
公开(公告)号：US6159870A
公开(公告)日：2000-12-12
申请号：US210411
申请日：1998-12-11
IPC分类号： H01L21/20 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/31604 , H01L21/31625 , H01L21/31629
摘要： A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.1 to 2.0 wt % fluorine.
摘要翻译： 在半导体器件上沉积氟化硼磷硅酸盐玻璃（FBPSG）作为最终或层间绝缘膜的方法。 纵横比大于6:1的间隙在约200托的亚大气压下，在约480℃的温度下填充基本上无空隙的FBPSG膜。 优选地，在该方法中使用的气态反应物包括具有臭氧/氧混合物的TEOS，FTES，TEPO和TEB。 硼和磷的掺杂浓度足够低，从而避免表面微晶缺陷和吸湿性。 较低纵横比间隙的沉积膜基本上无空隙，使得不需要膜的后续退火。 沉积在较高纵横比间隙中的膜在大约750℃或更低温度下退火，完全在大多数DRAM，逻辑和合并逻辑DRAM芯片的热预算内。 所得的FBPSG层含有小于或等于约5.0重量％的硼，小于约4.0重量％的磷和约0.1至2.0重量％的氟。
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50.发明授权Methods and apparatus for filling high aspect ratio structures with silicate glass 失效用硅酸盐玻璃填充高纵横比结构的方法和装置
公开(公告)号：US6077786A
公开(公告)日：2000-06-20
申请号：US854011
申请日：1997-05-08
IPC分类号： H01L21/316 , H01L21/762 , H01L21/311
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/02271 , H01L21/31625 , H01L21/76224
摘要： Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.
摘要翻译： 使用硅酸盐玻璃填充窄和/或高长宽比的间隙和沟槽在降低的温度下完成，并且通过在玻璃的热化学气相沉积中同时蚀刻玻璃而不进行回流，使得沉积速率将超过蚀刻速率相对较小 表面附近的净沉积速率随着沟槽或间隙的深度而增加。 通过在升高的温度下进行同时蚀刻和沉积工艺，但是在由先前执行的工艺形成的结构可以容忍的最大温度和热量预算范围内，将沉积的玻璃膜制成致密和稳定的。 氟可以以足够的浓度掺入到硅酸盐玻璃膜中作为掺杂剂以降低膜的介电常数。 也可以将磷和/或硼掺入到膜中，并且可以增强沟槽和间隙的无空隙填充。
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