公开(公告)号：US06665223B2

公开(公告)日：2003-12-16

申请号：US10278509

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06658523B2

公开(公告)日：2003-12-02

申请号：US09804221

申请日：2001-03-13

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

IPC分类号： G06F1200

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

公开(公告)号：US06522172B2

公开(公告)日：2003-02-18

申请号：US09812757

申请日：2001-03-20

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： H03K1903

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A circuit having a data input pin for receiving a data signal, a clock input for receiving a clock signal and having a low setup time and a zero hold time is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal. Alternatively, multiple data paths may be provided as well as multiple charge accumulating devices so that data signals representative of the sampled data may be output on both the rising and the falling edge of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time and of the type useful for receiving signals from a high speed bus is also disclosed.

摘要翻译： 具有用于接收数据信号的数据输入引脚的电路，用于接收时钟信号并具有低建立时间和零保持时间的时钟输入包括用于将采样装置周期性地连接到数据输入引脚的输入级 响应时钟信号。 响应于时钟信号的评估阶段评估设备在与数据输入引脚断开连接时收集的电荷。 评估阶段产生代表采样电荷的信号。 响应于时钟信号和产生的信号的输出级输出表示采样数据信号的数据信号。 电路可以具有单个数据路径和单个电荷累积装置，使得表示采样数据信号的输出信号在时钟信号的上升沿或下降沿都可用。 或者，可以提供多个数据路径以及多个电荷累积装置，使得表示采样数据的数据信号可以在时钟信号的上升沿和下降沿两者上输出。 该电路可以作为锁存器或寄存器来操作。 还公开了一种操作具有零保持时间的数据采集和保持电路以及用于从高速总线接收信号的类型的方法。

公开(公告)号：US06480031B2

公开(公告)日：2002-11-12

申请号：US10056384

申请日：2002-01-24

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： H03K19096

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A circuit having a data pin, an input pin for receiving a clock signal and having a zero hold time, is comprised of a sampling transistor for collecting charge at the data pin during a setup time defined by the clock signal; a device for isolating the sampling transistor from the data pin in response to the clock signal; and an output stage for outputting a logic signal in response to the charge sampled by the sampling transistor and the clock signal. The circuit may have an inverter for producing the complement of the clock signal, and the device for isolating may include a multiplexer responsive to the clock signal and the complement of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time is also disclosed.

摘要翻译： 具有数据引脚的电路，用于接收时钟信号并具有零保持时间的输入引脚包括用于在由时钟信号定义的建立时间期间在数据引脚处收集电荷的采样晶体管; 用于响应于时钟信号将采样晶体管与数据引脚隔离的装置; 以及输出级，用于响应于由采样晶体管采样的电荷和时钟信号而输出逻辑信号。 电路可以具有用于产生时钟信号的补码的反相器，并且用于隔离的装置可以包括响应于时钟信号和时钟信号的补码的多路复用器。 该电路可以作为锁存器或寄存器来操作。 还公开了具有零保持时间的操作数据采集和保持电路的方法。

公开(公告)号：US07577212B2

公开(公告)日：2009-08-18

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H03K9/00

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US07457172B2

公开(公告)日：2008-11-25

申请号：US11999383

申请日：2007-12-04

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US07031215B2

公开(公告)日：2006-04-18

申请号：US11031437

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C11/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06909196B2

公开(公告)日：2005-06-21

申请号：US10178172

申请日：2002-06-21

申请人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

发明人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：US20050122789A1

公开(公告)日：2005-06-09

申请号：US11031437

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C5/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US20050094432A1

公开(公告)日：2005-05-05

申请号：US11001231

申请日：2004-12-01

申请人： Brian Johnson ,  Brent Keeth ,  Jeffery Janzen ,  Troy Manning ,  Chris Martin

发明人： Brian Johnson ,  Brent Keeth ,  Jeffery Janzen ,  Troy Manning ,  Chris Martin

IPC分类号： G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C11/00

CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。