公开(公告)号：US20100159688A1

公开(公告)日：2010-06-24

申请号：US12454322

申请日：2009-05-15

Applicant: Darrell Rinerson ,  Robin Cheung

Inventor： Darrell Rinerson ,  Robin Cheung

IPC: H01L21/768

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

公开(公告)号：US06842659B2

公开(公告)日：2005-01-11

申请号：US09939073

申请日：2001-08-24

Applicant: Suketu Parikh ,  Robin Cheung

Inventor： Suketu Parikh ,  Robin Cheung

IPC: G05B19/418 ,  H01L21/66 ,  G06F19/00

CPC classification number: H01L22/20 ,  G05B19/4187 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/205 ,  Y02P90/22

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

Abstract translation: 一种用于在多步骤处理系统内执行工具内监控和控制的方法和装置。 该方法通过独立操作处理工具处理工件来监视工件的处理，并为各种独立操作的加工工具生成控制参数，以优化工件的加工。 更具体地，该设备提供位于多个半导体晶片处理工具中的每一个之间的计量站，使得当它们从一个工具传递到另一个工具提供内部工具监视时，可以对晶片进行测量。 由计量站收集的数据耦合到度量数据分析器，该测量数据分析器确定是否应该调整多个晶片处理工具中的任何一个以改善整个晶片的处理。 因此，测量数据分析仪的输出提供控制参数以处理连接到半导体晶片处理系统内的每个工具的控制器连接的控制器。 因此，计量站和度量数据分析仪的操作提供前馈和反馈数据，以基于在计量站内收集的某些信息来控制工具。

公开(公告)号：US06818066B2

公开(公告)日：2004-11-16

申请号：US09850841

申请日：2001-05-07

Applicant: Robin Cheung

Inventor： Robin Cheung

IPC: C23C880

CPC classification number: H01L21/76849 ,  H01L21/288 ,  Y10S134/902

Abstract: A system and method for treating a substrate by integrating the annealing of a metal-containing layer on a substrate as part of a chemical mechanical polishing process. In one embodiment, a system for treating a substrate generally includes an annealing station incorporated into a chemical mechanical polishing processing system that includes a deposition station utilized to form a metal-containing layer on the substrate.

Abstract translation: 作为化学机械抛光工艺的一部分，通过将基板上的含金属层的退火结合在一起来处理基板的系统和方法。 在一个实施例中，用于处理衬底的系统通常包括结合到化学机械抛光处理系统中的退火站，其包括用于在衬底上形成含金属层的沉积站。

公开(公告)号：US06477787B2

公开(公告)日：2002-11-12

申请号：US10073762

申请日：2002-02-11

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: F26B700

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.

公开(公告)号：US06400030B1

公开(公告)日：2002-06-04

申请号：US09583817

申请日：2000-05-30

Applicant: Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

Inventor： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

IPC: H01L2348

CPC classification number: H01L21/76897 ,  H01L21/76802

Abstract: An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

Abstract translation: 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

公开(公告)号：US06357143B2

公开(公告)日：2002-03-19

申请号：US09909915

申请日：2001-07-20

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: F26B700

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.

Abstract translation: 一种用于加热和冷却基底的方法和装置。 提供了一种室，其包括适于加热位于加热机构附近的基板的加热机构，与加热机构间隔开并适于冷却位于冷却机构附近的基板的冷却机构，以及适于将基板 靠近加热机构的位置和靠近冷却机构的位置。

公开(公告)号：US06245670B1

公开(公告)日：2001-06-12

申请号：US09253480

申请日：1999-02-19

Applicant: Robin Cheung ,  Sergey Lopatin

Inventor： Robin Cheung ,  Sergey Lopatin

IPC: H01L214763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76877

Abstract: A method for effectively filling a dual damascene opening having a via hole and a trench that are contiguous openings uses a two step deposition process. The method includes a step of filling the via hole by electroless deposition of a first conductive material into the via hole. A second conductive material is at a bottom wall of the via hole, and the second conductive material at the bottom wall of the via hole acts as an autocatalytic surface during the electroless deposition of the first conductive material within the via hole. The method also includes the step of depositing a seed layer of a third conductive material to cover walls of the trench and includes the step of filling the trench by electroplating deposition of the third conductive material from the seed layer into the trench. The present invention may be used to particular advantage for small geometry integrated circuits when the conductive material filling the via hole and the trench is copper. By first filling the via hole using electroless deposition, void formation and poor via contact is prevented. In addition, the more widely available and easily manufacturable electroplating deposition process is still used for filling the trench.

Abstract translation: 一种用于有效地填充具有通孔和作为连续开口的沟槽的双镶嵌开口的方法使用两步沉积工艺。 该方法包括通过将第一导电材料无电沉积到通孔中来填充通孔的步骤。 第二导电材料位于通孔的底壁处，并且在第一导电材料在通孔内的无电沉积期间，通孔的底壁处的第二导电材料用作自催化表面。 该方法还包括沉积第三导电材料的种子层以覆盖沟槽的壁的步骤，并且包括通过电镀将第三导电材料从晶种层沉积到沟槽中来填充沟槽的步骤。 当填充通孔和沟槽的导电材料是铜时，本发明可以用于小几何形状集成电路的特别有利。 通过首先使用无电沉积填充通孔，防止空隙形成和差的通孔接触。 此外，仍然使用更广泛可用且容易制造的电镀沉积工艺来填充沟槽。

公开(公告)号：US6083842A

公开(公告)日：2000-07-04

申请号：US253479

申请日：1999-02-19

Applicant: Robin Cheung ,  Sergey Lopatin

Inventor： Robin Cheung ,  Sergey Lopatin

IPC: H01L21/768 ,  H01L21/302

CPC classification number: H01L21/76852 ,  H01L21/76843 ,  H01L21/76885

Abstract: A method for efficiently fabricating a via plug having high aspect ratio within an insulating layer with a diffusion barrier layer effectively surrounding the via plug. The method includes the steps of depositing a via photoresist layer over a first metal line of a first conductive material and etching a via hole in the via photoresist layer. The first conductive material of the first metal line is exposed at a bottom wall of the via hole. A via plug of a second conductive material is deposited into the via hole, and the via plug makes a conductive path with the first metal line. The via photoresist layer is then removed such that any side wall of the via plug is exposed. A first diffusion barrier layer is then deposited onto any exposed surface of the second conductive material of the via plug. A via insulating layer is then spin-coated to surround the via plug and a trench insulating layer is also deposited over the via insulating layer. A trench is then etched over the via plug having the first diffusion barrier layer, and the via plug with the first diffusion barrier layer is exposed as part of a bottom wall of the trench. A second diffusion barrier layer is then deposited onto the walls of the trench, and a third conductive material is deposited into the trench to form a second metal line. The second metal line makes a conductive path with the second conductive material of the via plug. Thus, the present invention avoids the prior art method of depositing a diffusion barrier layer into the via hole within a via insulating layer before filling the via hole with the via plug. With the present invention, a via plug with high aspect ratio may be efficiently formed with the diffusion barrier layer effectively surrounding the via plug.

Abstract translation: 一种用于在绝缘层内有效地制造具有高纵横比的通孔的方法，其中扩散阻挡层有效围绕通孔塞。 该方法包括以下步骤：在第一导电材料的第一金属线上沉积通孔光致抗蚀剂层，并蚀刻通孔光致抗蚀剂层中的通孔。 第一金属线的第一导电材料暴露在通孔的底壁处。 第二导电材料的通孔插入到通孔中，并且通孔插头与第一金属线形成导电路径。 然后去除通孔光致抗蚀剂层，使得通孔塞的任何侧壁暴露。 然后将第一扩散阻挡层沉积到通孔塞的第二导电材料的任何暴露的表面上。 然后将通孔绝缘层旋涂以包围通孔塞，并且沟槽绝缘层也沉积在通孔绝缘层上。 然后在具有第一扩散阻挡层的通孔上蚀刻沟槽，并且具有第一扩散阻挡层的通孔插塞作为沟槽底壁的一部分暴露。 然后将第二扩散阻挡层沉积在沟槽的壁上，并且将第三导电材料沉积到沟槽中以形成第二金属线。 第二金属线与通孔塞的第二导电材料形成导电路径。 因此，本发明避免了在使用通孔插塞填充通孔之前在通孔绝缘层中的通孔中沉积扩散阻挡层的现有技术方法。 利用本发明，可以有效地形成具有高纵横比的通孔，扩散阻挡层有效地围绕过孔塞。

公开(公告)号：US6048802A

公开(公告)日：2000-04-11

申请号：US905978

申请日：1997-08-05

Applicant: Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

Inventor： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜 绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。 现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。 在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

公开(公告)号：US6033982A

公开(公告)日：2000-03-07

申请号：US149208

申请日：1998-09-08

Applicant: Sergey Lopatin ,  Robin Cheung

Inventor： Sergey Lopatin ,  Robin Cheung

IPC: H01L21/316 ,  H01L21/768 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/326

CPC classification number: H01L21/76888 ,  H01L21/31687 ,  H01L21/76885 ,  Y10S257/915 ,  Y10S428/901 ,  Y10T428/12493 ,  Y10T428/12597 ,  Y10T428/12611

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor metal oxide.

Abstract translation: 提供一种形成导线结构的方法。 在基板表面上形成粘合层。 种子层形成在粘合层上。 在种子层上形成导体以形成部分完整的结构。 部分完整的结构暴露于电解质并进行阳极氧化处理。 种子层和导体的一部分的至少一部分分别转化为晶种层金属氧化物和导体金属氧化物。 粘合层的至少一部分被转化为粘合层金属氧化物，并且导体的另一部分转变为导体金属氧化物。 在种子层金属氧化物和导体金属氧化物上形成外部金属层。