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    Method for manufacturing semiconductors with self-aligning vias
    1.
    发明授权
    Method for manufacturing semiconductors with self-aligning vias 失效
    具有自对准通孔的半导体制造方法

    公开(公告)号：US6124201A

    公开(公告)日：2000-09-26

    申请号：US097126

    申请日：1998-06-12

    申请人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

    发明人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

    IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/76802

    摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

    摘要翻译： 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

    Self-aligning vias for semiconductors
    2.
    发明授权
    Self-aligning vias for semiconductors 有权
    半导体自对准通孔

    公开(公告)号：US06400030B1

    公开(公告)日：2002-06-04

    申请号：US09583817

    申请日：2000-05-30

    申请人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

    发明人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

    IPC分类号： H01L2348

    CPC分类号： H01L21/76897 ,  H01L21/76802

    摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

    摘要翻译： 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

    Cure process for manufacture of low dielectric constant interlevel dielectric layers
    4.
    发明授权
    Cure process for manufacture of low dielectric constant interlevel dielectric layers 有权
    用于制造低介电常数层间电介质层的固化工艺

    公开(公告)号：US06200913B1

    公开(公告)日：2001-03-13

    申请号：US09191040

    申请日：1998-11-12

    申请人： Lu You ,  Simon S. Chan ,  John Iacoponi ,  Richard J. Huang ,  Robin Cheung

    发明人： Lu You ,  Simon S. Chan ,  John Iacoponi ,  Richard J. Huang ,  Robin Cheung

    IPC分类号： H01L21324

    CPC分类号： H01L21/02134 ,  H01L21/02282 ,  H01L21/31058 ,  H01L21/3124

    摘要： This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.

    摘要翻译： 本发明包括改进旋涂电介质层固化的方式。 半导体晶片被涂覆有用于旋涂电介质材料的前体，并且在溶液变薄并均匀之后，将晶片放置在固化炉中，任选地包含惰性气体，并预热到低于该温度的温度 在半导体晶片中不产生热机械应力和/或氧化。 然后将固化炉内的温度升高至固化温度，然后缓慢降低温度，以防止形成应力裂纹和薄膜的介电功能的损失。 本发明的固化方法可用于制造采用各种旋涂材料的半导体器件。

    Simplified dual damascene process for multi-level metallization and interconnection structure
    5.
    发明授权
    Simplified dual damascene process for multi-level metallization and interconnection structure 失效
    用于多层次金属化和互连结构的简化双镶嵌工艺

    公开(公告)号：US5635423A

    公开(公告)日：1997-06-03

    申请号：US320516

    申请日：1994-10-11

    申请人： Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

    发明人： Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

    摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

    摘要翻译： 通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。 在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。 然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。 沟槽和通孔然后同时填充导电材料。

    Cu damascene interconnections using barrier/capping layer
    7.
    发明授权
    Cu damascene interconnections using barrier/capping layer 有权
    铜镶嵌互连使用屏障/覆盖层

    公开(公告)号：US06689684B1

    公开(公告)日：2004-02-10

    申请号：US09783619

    申请日：2001-02-15

    申请人： Lu You ,  Fei Wang ,  Richard J. Huang

    发明人： Lu You ,  Fei Wang ,  Richard J. Huang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76844 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76862 ,  H01L21/76865

    摘要： Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD corners, the exposed barrier layer portion is removed and redeposited to form a liner on the side surfaces of the dielectric layer defining the opening, thereby avoiding Cu redeposition on, and/or penetration through, the side surfaces of the dielectric layer.

    摘要翻译： 通过用诸如Ta或TaN的阻挡材料替换上覆电介质层（例如ILD）中的开口底部的覆盖层的一部分，形成具有改进的可靠性的互连件。 在Ar溅射蚀刻以绕过ILD拐角期间，暴露的阻挡层部分被去除并重新沉积以在限定开口的电介质层的侧表面上形成衬垫，从而避免Cu再沉积和/或穿透侧面 的介电层。