公开(公告)号：US20100234975A1

公开(公告)日：2010-09-16

申请号：US12402124

申请日：2009-03-11

Applicant: Chih-Jen Wu ,  Chen-Ming Huang ,  An-Chun Tu

Inventor： Chih-Jen Wu ,  Chen-Ming Huang ,  An-Chun Tu

IPC: G05B13/02 ,  G06F17/00

CPC classification number: H01L21/28026 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.

Abstract translation: 公开了一种制造具有改进性能的集成电路的方法。 该方法包括提供基底; 执行多个处理以在所述衬底上形成栅极堆叠，其中所述栅极堆叠包括栅极层; 在所述多个处理中的至少一个处理之后测量所述栅极层的晶粒尺寸; 确定所测量的晶粒尺寸是否在目标范围内; 以及如果所述测量的所述栅极层的晶粒尺寸不在所述目标范围内，则修改所述多个处理中的至少一个处理的配方。

公开(公告)号：US07569909B2

公开(公告)日：2009-08-04

申请号：US11745980

申请日：2007-05-08

Applicant: Chen-Ming Huang

Inventor： Chen-Ming Huang

IPC: H01L29/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括衬底。 介电层形成在衬底上，并且相变材料层嵌入电介质层中。 第一导电电极也嵌入电介质层中以穿透相变材料层并且垂直于电介质层的顶表面延伸。

公开(公告)号：US07557402B2

公开(公告)日：2009-07-07

申请号：US11599930

申请日：2006-11-15

Applicant: Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

Inventor： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC: H01L29/34

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract translation: 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。

公开(公告)号：US20070063248A1

公开(公告)日：2007-03-22

申请号：US11599930

申请日：2006-11-15

Applicant: Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

Inventor： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC: H01L29/76

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract translation: 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。

公开(公告)号：US20050079672A1

公开(公告)日：2005-04-14

申请号：US10685127

申请日：2003-10-14

Applicant: Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

Inventor： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/32139 ,  H01L27/115

Abstract: A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Abstract translation: 一种分裂栅FET字线电极结构及其形成方法，包括改进的多晶硅蚀刻工艺，包括提供包括第一裸露多晶硅部分和相邻氧化物部分的半导体晶片工艺表面; 在所述暴露的多晶硅部分上形成第一氧化物层; 在第一暴露的多晶硅部分和相邻的氧化物部分上覆盖多晶硅层; 在所述多晶硅层上形成硬掩模层; 执行多步反应离子蚀刻（RIE）工艺以蚀刻穿过硬掩模层并蚀刻穿过多晶硅层的厚度部分，以形成与具有向上突出的外部多晶硅栅栏部分的氧化物部分相邻的第二多晶硅部分; 使所述半导体晶片工艺表面与HF水溶液接触; 并且执行下游等离子体蚀刻工艺以去除多晶硅栅栏部分。

公开(公告)号：US06878986B2

公开(公告)日：2005-04-12

申请号：US10403137

申请日：2003-03-31

Applicant: Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

Inventor： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.

Abstract translation: 一种存储单元，包括具有源极区域的衬底; 浮置栅极结构，设置在所述衬底上并与所述源极区域相关联; 以及源耦合增强结构，其覆盖所述浮栅结构的暴露部分并延伸到所述源极区。 闪存单元可以以包括以下步骤的方法制造：在衬底上形成浮置栅极结构; 在所述浮动栅极结构的暴露部分上形成所述源耦合增强结构; 以及在衬底中形成源区。

公开(公告)号：US06849546B1

公开(公告)日：2005-02-01

申请号：US10700779

申请日：2003-11-04

Applicant: An-Chun Tu ,  Chen-Ming Huang

Inventor： An-Chun Tu ,  Chen-Ming Huang

IPC: H01L21/336 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L29/6659 ,  H01L21/76801 ,  H01L29/665

Abstract: A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.

公开(公告)号：US06649489B1

公开(公告)日：2003-11-18

申请号：US10366207

申请日：2003-02-13

Applicant: Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

Inventor： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

IPC: H01L2176

CPC classification number: H01L21/76232

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

Abstract translation: 描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。 衬底上设置介电层，并在电介质层上设置多晶硅层。 形成浅沟槽，其延伸穿过多晶硅和电介质层进入衬底。 绝缘材料用于填充沟槽，然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。 沉积保形缓冲层，其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。 将缓冲层回蚀刻以暴露绝缘层，并且通过等离子体蚀刻去除多晶硅。 由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽，从而增加蚀刻工艺窗口。

公开(公告)号：US06638409B1

公开(公告)日：2003-10-28

申请号：US10152471

申请日：2002-05-21

Applicant: Chen-Ming Huang ,  Li-Chuen Cheng ,  Hung-Jen Lin ,  Chih-Chen Ku ,  San-Sun Yang

Inventor： Chen-Ming Huang ,  Li-Chuen Cheng ,  Hung-Jen Lin ,  Chih-Chen Ku ,  San-Sun Yang

IPC: C25D2118

CPC classification number: C25D21/06 ,  C25D21/12 ,  C25D21/18

Abstract: A real-time and in-line process control system maintains stable plating performance in copper electrochemical plating IC devices by using a real time, on-line programmable controller. Two or more valves to direct the flow of the electrolyte from the electroplating cell back to the reservoir connect an alternative carbon-filter as well as a mirco-filter. The programmable controller controls the operation of at least two in-line valves to direct the flow of the electrolyte within the system.

Abstract translation: 实时和在线过程控制系统通过使用实时在线可编程控制器在铜电化学电镀IC器件中保持稳定的电镀性能。 两个或更多个阀将电解液从电镀池引导回储存器，连接另一个碳过滤器以及微过滤器。 可编程控制器控制至少两个直列阀的操作以引导系统内的电解质的流动。