公开(公告)号：US20100084766A1

公开(公告)日：2010-04-08

申请号：US12247568

申请日：2008-10-08

申请人： Chih-Chao Yang ,  Conal E. Murray

发明人： Chih-Chao Yang ,  Conal E. Murray

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss.

摘要翻译： 提供了包括表面修复材料（例如贵金属或贵金属合金）的半导体互连结构，其填充位于导电材料内的空心金属相关缺陷。 用表面修复材料填充中空金属相关缺陷改善了结构的电迁移（EM）可靠性以及降低了在线缺陷相关产量损失。

公开(公告)号：US20090278260A1

公开(公告)日：2009-11-12

申请号：US12115817

申请日：2008-05-06

申请人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/4763 ,  G06F9/45

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other.

摘要翻译： 提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连，提供IC互连的设计结构和IC互连的制造方法。 该结构具有电迁移免疫性和设计冗余性，其包括并列布置的多根线，并且每条线都涂有衬里材料。 电线的两个相互物理接触。

公开(公告)号：US06972209B2

公开(公告)日：2005-12-06

申请号：US10306534

申请日：2002-11-27

申请人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

发明人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

公开(公告)号：US06768111B1

公开(公告)日：2004-07-27

申请号：US10663552

申请日：2003-09-16

申请人： Oliver C. Wells ,  Lynne M. Gignac ,  Jonathan L. Rullan ,  Conal E. Murray

发明人： Oliver C. Wells ,  Lynne M. Gignac ,  Jonathan L. Rullan ,  Conal E. Murray

IPC分类号： G01N2300

CPC分类号： G01N23/2251

摘要： A method of measurement of topographic features on a surface of a substrate is presented, wherein a focused beam of particles falls onto the surface of the substrate, and backscattered particles are detected with a particle detector. An opaque material is interposed between the surface and the detector, and the position of the shadow of an edge of the opaque material on the detector is recorded. The relative position of the edge and the surface of the substrate is then determined, and the topography of the surface determined as the particle beam and the substrate are moved with respect to one another.

摘要翻译： 提出了一种测量衬底表面上的地形特征的方法，其中聚焦的粒子束落在衬底的表面上，用颗粒检测器检测背散射的颗粒。 在表面和检测器之间插入不透明材料，并记录不透明材料边缘在检测器上的位置。 然后确定边缘和基板的表面的相对位置，并且确定为粒子束和基板的表面的形貌相对于彼此移动。

公开(公告)号：US20110133163A1

公开(公告)日：2011-06-09

申请号：US12631203

申请日：2009-12-04

申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Conal E. Murray ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Conal E. Murray ,  Jeffrey W. Sleight

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/7845 ,  H01L29/78696

摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.

摘要翻译： 提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属 多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

公开(公告)号：US07871935B2

公开(公告)日：2011-01-18

申请号：US12108119

申请日：2008-04-23

申请人： Chih-Chao Yang ,  Conal E. Murray

发明人： Chih-Chao Yang ,  Conal E. Murray

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L23/53238 ,  H01L21/02074 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure which has a high leakage resistance and substantially no metallic residues and no physical damage present at an interface between the interconnect dielectric and an overlying dielectric capping layer. The interconnect structure of the invention also has an interface between each conductive feature and the overlying dielectric capping layer that is substantially defect-free. The interconnect structure of the invention includes a non-plasma deposited dielectric capping layer which is formed utilizing a process including a thermal and chemical-only pretreatment step that removes surface oxide from atop each of the conductive features as well as metallic residues from atop the interconnect dielectric material. Following this pretreatment step, the dielectric capping layer is deposited.

摘要翻译： 本发明提供一种互连结构，其具有高的耐漏电性，并且基本上没有金属残留物，并且在互连电介质和上覆电介质覆盖层之间的界面处不存在物理损伤。 本发明的互连结构还具有每个导电特征和基本上无缺陷的上覆电介质覆盖层之间的界面。 本发明的互连结构包括非等离子体沉积的介电覆盖层，其使用包括热和仅化学预处理步骤的方法形成，该步骤从每个导电特征顶部以及互连上方的金属残留物去除表面氧化物 介电材料。 在该预处理步骤之后，沉积介电覆盖层。

公开(公告)号：US07846834B2

公开(公告)日：2010-12-07

申请号：US12025297

申请日：2008-02-04

申请人： Chih-Chao Yang ,  Conal E. Murray

发明人： Chih-Chao Yang ,  Conal E. Murray

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76835 ,  H01L21/76843

摘要： A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.

摘要翻译： 提供了一种半导体结构，其包括下互连级，其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平，其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触 通过锚定区域。 此外，本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。 因此，第二电介质材料在与导电填充线相邻的区域中不包括受损区域。 还提供了一种形成这种互连结构的方法。

公开(公告)号：US20090109722A1

公开(公告)日：2009-04-30

申请号：US11928258

申请日：2007-10-30

申请人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G06F17/5045 ,  H04L29/08072 ,  H04L45/00

摘要： The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 本发明提供了一种可再编程的电可熔熔丝和相关的设计结构。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US07456098B2

公开(公告)日：2008-11-25

申请号：US11403332

申请日：2006-04-13

申请人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

发明人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

IPC分类号： H01L21/4763

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械构造尖端。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US20080251284A1

公开(公告)日：2008-10-16

申请号：US12098895

申请日：2008-04-07

申请人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E. Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardus Fransiscus Maria Standaert ,  Xiao Hu Liu

发明人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E. Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardus Fransiscus Maria Standaert ,  Xiao Hu Liu

IPC分类号： H05K1/16

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

摘要翻译： 一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装 层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生列。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。