公开(公告)号：US20080251284A1

公开(公告)日：2008-10-16

申请号：US12098895

申请日：2008-04-07

申请人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E. Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardus Fransiscus Maria Standaert ,  Xiao Hu Liu

发明人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E. Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardus Fransiscus Maria Standaert ,  Xiao Hu Liu

IPC分类号： H05K1/16

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

摘要翻译： 一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装 层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生列。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。

公开(公告)号：US07947907B2

公开(公告)日：2011-05-24

申请号：US12098895

申请日：2008-04-07

申请人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardos Standaert ,  Xiao Hu Liu

发明人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardos Standaert ,  Xiao Hu Liu

IPC分类号： H05K1/03

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

摘要翻译： 一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装 层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生柱。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。

公开(公告)号：US07371684B2

公开(公告)日：2008-05-13

申请号：US11130078

申请日：2005-05-16

申请人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E. Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Maria Standaert ,  Xiao Hu Liu

发明人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E. Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Maria Standaert ,  Xiao Hu Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

摘要翻译： 一种用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡一部分 图案，然后将图案的未封闭部分转印到基底叠层中。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。 要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。 提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

公开(公告)号：US07084479B2

公开(公告)日：2006-08-01

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

发明人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

公开(公告)号：US20110163446A1

公开(公告)日：2011-07-07

申请号：US12983885

申请日：2011-01-04

申请人： Satyanarayana Venkata Nitta ,  Sampath PURUSHOTHAMAN ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth

发明人： Satyanarayana Venkata Nitta ,  Sampath PURUSHOTHAMAN ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth

IPC分类号： H01L23/48

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed.

摘要翻译： 在具有电介质层和铜互连的衬底上产生气隙的结构和方法，其中的亚光刻穿孔在整个晶片结构中以宏观水平和微观级别排列，并且铜层的顶层 互连不暴露。

公开(公告)号：US20080122106A1

公开(公告)日：2008-05-29

申请号：US11518773

申请日：2006-09-11

申请人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

发明人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

摘要翻译： 在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

公开(公告)号：US06737725B2

公开(公告)日：2004-05-18

申请号：US10144574

申请日：2002-05-13

申请人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

发明人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

IPC分类号： H01L2900

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885

摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

摘要翻译： 一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。 本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在 至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

公开(公告)号：US20080166870A1

公开(公告)日：2008-07-10

申请号：US11570014

申请日：2005-05-23

申请人： Elbert Emin Huang ,  Hyungjun Kim ,  Robert Dennis Miller ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman

发明人： Elbert Emin Huang ,  Hyungjun Kim ,  Robert Dennis Miller ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

摘要翻译： 通过包括通过原子层沉积或基于超临界流体的方法沉积薄的共形钝化介质和/或扩散阻挡盖和/或硬掩模的方法来制造互连结构。

公开(公告)号：US06413852B1

公开(公告)日：2002-07-02

申请号：US09652754

申请日：2000-08-31

申请人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

发明人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

IPC分类号： H01L218234

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885

摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

摘要翻译： 一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。 本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在 至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

公开(公告)号：US07790601B1

公开(公告)日：2010-09-07

申请号：US12561651

申请日：2009-09-17

申请人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

发明人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  H01L21/31144

摘要： Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

摘要翻译： 公开了一种在互连中形成气隙的积分方法的过程。 在半导体衬底上的金属布线层的顶部上沉积介电覆盖层，接着是牺牲介电层和图案转移层。 图案通过图案转移层，牺牲介电层，电介质盖层转移到金属布线层中。 牺牲介电层的存在有助于控制电介质盖层的厚度和轮廓，这进而影响互连的可靠性。