公开(公告)号：US10037493B2

公开(公告)日：2018-07-31

申请号：US14520139

申请日：2014-10-21

Applicant: D-Wave Systems Inc.

Inventor： Richard G. Harris ,  Mohammad H. S. Amin ,  Anatoly Smirnov

IPC: G06F17/00 ,  G06N99/00 ,  H03K3/38 ,  H03K19/195 ,  G11C11/44

CPC classification number: G06N10/00 ,  G11C11/44 ,  H03K3/38 ,  H03K19/1952

Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

公开(公告)号：US20170162778A1

公开(公告)日：2017-06-08

申请号：US15438296

申请日：2017-02-21

Applicant: D-Wave Systems Inc.

Inventor： Richard G. Harris ,  Andrew J. Berkley ,  Jan Johansson ,  Mark Johnson ,  Mohammad Amin ,  Paul I. Bunyk

IPC: H01L39/22 ,  G06N99/00

CPC classification number: H01L39/223 ,  B82Y10/00 ,  G06N99/002 ,  H01L27/18

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

公开(公告)号：US09152923B2

公开(公告)日：2015-10-06

申请号：US13958339

申请日：2013-08-02

Applicant: D-Wave Systems Inc.

Inventor： Richard G. Harris ,  Andrew J. Berkley ,  Jan Johansson ,  Mark Johnson ,  Mohammad Amin ,  Paul I. Bunyk

IPC: G06N99/00 ,  B82Y10/00 ,  H01L39/22

CPC classification number: H01L39/223 ,  B82Y10/00 ,  G06N99/002 ,  H01L27/18

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract translation: 装置和方法使得能够对量子处理器的超导元件中的不期望的差异进行主动补偿。 量子位可以包括主复合约瑟夫逊结（CJJ）结构，其可以包括至少第一次级CJJ结构，以能够补偿主CJJ结构中的约瑟夫逊结不对称性。 量子位可以包括与第一CJJ结构并联耦合以提供可调电容的串联LC电路。 量子比特控制系统可以包括用于调整量子比特环的电感的装置，例如感应耦合到量子位循环并由编程接口控制的可调谐耦合器，或与量子位循环串联耦合并由编程接口控制的CJJ结构 。

公开(公告)号：US20140137571A1

公开(公告)日：2014-05-22

申请号：US14086697

申请日：2013-11-21

Applicant: D-Wave Systems Inc.

Inventor： Jacob Craig Petroff ,  Richard G. Harris

IPC: B01D8/00

CPC classification number: B01D8/00 ,  F25B9/10 ,  F25B9/12 ,  F25B9/145 ,  F25D19/006

Abstract: Systems and methods for improving the performance of dilution refrigeration systems are described. Filters and traps employed in the helium circuit of a dilution refrigerator may be modified to improve performance. Some traps may be designed to harness cryocondensation as opposed to cryoadsorption. A cryocondensation trap employs a cryocondensation surface having a high thermal conductivity and a high specific heat with a binding energy that preferably matches at least one contaminant but does not match helium. Multiple traps may be coupled in series in the helium circuit, with each trap designed to trap a specific contaminant or set of contaminants. Both cryocondensation and cryoadsorption may be exploited among multiple traps.

Abstract translation: 描述了用于改善稀释制冷系统性能的系统和方法。 可以修改在稀释制冷机的氦回路中使用的过滤器和捕集器，以改善性能。 一些陷阱可能被设计为利用低温冷冻而不是冷冻吸收。 低温冷凝阱采用具有高热导率和高比热的冷凝表面，其结合能优选与至少一种污染物匹配但不匹配氦。 多个陷阱可以串联耦合在氦气回路中，每个捕集阱被设计成捕获特定的污染物或一组污染物。 可以在多个陷阱中利用冷冻和低温吸收。

公开(公告)号：US20130313526A1

公开(公告)日：2013-11-28

申请号：US13958339

申请日：2013-08-02

Applicant: D-Wave Systems Inc.

Inventor： Richard G. Harris ,  Andrew J. Berkley ,  Jan Johansson ,  Mark Johnson ,  Mohammad Amin ,  Paul I. Bunyk

IPC: G06N99/00 ,  H01L39/22

CPC classification number: H01L39/223 ,  B82Y10/00 ,  G06N99/002 ,  H01L27/18

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

公开(公告)号：US12165003B2

公开(公告)日：2024-12-10

申请号：US17199079

申请日：2021-03-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Richard G. Harris

IPC: G06N10/00 ,  G06F17/14 ,  G06F17/16 ,  G06F30/23

Abstract: A system and method of implementing finite element modeling on a quantum processor is discussed. A representation of a computational problem including a boundary value problem and problem grid points is received by one or more processors. The problem grid points are mapped to a Hilbert space of the qubits of the quantum processor. The boundary value problem is transformed into a problem Hamiltonian. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the problem Hamiltonian. The wavefunction amplitudes of the final state are measured, and the wavefunction amplitudes of the final state are mapped onto the problem grid points based on the Hilbert space of the qubits.

公开(公告)号：US11957065B2

公开(公告)日：2024-04-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H10N60/01 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N60/85 ,  H10N69/00

CPC classification number: H10N60/0156 ,  H01L21/76891 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53285 ,  H10N60/85 ,  H10N69/00

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11790259B2

公开(公告)日：2023-10-17

申请号：US16996355

申请日：2020-08-18

Applicant: D-WAVE SYSTEMS INC.

Inventor： Richard G. Harris

IPC: G06N10/00 ,  G06F15/78 ,  G06N10/40

CPC classification number: G06N10/00 ,  G06F15/7867 ,  G06N10/40

Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

公开(公告)号：US11038095B2

公开(公告)日：2021-06-15

申请号：US16481788

申请日：2018-01-31

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L27/18 ,  H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US20210073667A1

公开(公告)日：2021-03-11

申请号：US16996355

申请日：2020-08-18

Applicant: D-WAVE SYSTEMS INC.

Inventor： Richard G. Harris

IPC: G06N10/00 ,  G06F15/78

Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.