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    Methods of forming semiconductor devices having buried oxide patterns
    41.
    发明授权
    Methods of forming semiconductor devices having buried oxide patterns 有权
    形成具有掩埋氧化物图案的半导体器件的方法

    公开(公告)号：US07320908B2

    公开(公告)日：2008-01-22

    申请号：US11072103

    申请日：2005-03-04

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Jong-Wook Lee ,  In-Soo Jung ,  Deok-Hyung Lee

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Jong-Wook Lee ,  In-Soo Jung ,  Deok-Hyung Lee

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7851 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66621

    摘要： Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.

    摘要翻译： 提供了形成半导体器件的方法。 蚀刻半导体衬底，使得半导体衬底限定沟槽和初步活性图案。 沟槽具有地板和侧壁。 绝缘层设置在地板上，并且沟槽的侧壁和间隔件形成在绝缘层上，使得间隔件位于沟槽的侧壁和沟槽底部的一部分上。 绝缘层在沟槽的地板上移除并且在间隔物的下面被移除，使得沟槽的底部的一部分至少部分地露出，间隔物与沟槽的底部间隔开，并且预活性图案的一部分 部分暴露。 部分地去除预活性图案的暴露部分的一部分以提供在间隔物下方限定凹陷部分的活性图案。 在活性图案的凹部中形成掩埋绝缘层。 还提供了相关设备。

    Fin field effect transistors with low resistance contact structures
    42.
    发明授权
    Fin field effect transistors with low resistance contact structures 有权
    具有低电阻接触结构的Fin场效应晶体管

    公开(公告)号：US07385237B2

    公开(公告)日：2008-06-10

    申请号：US11076185

    申请日：2005-03-09

    申请人： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

    发明人： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

    IPC分类号： H01L29/08

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

    摘要翻译： 提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层， 基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。 导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。 在其它实施例中，导电层可以包括接触垫。

    Fin field effect transistors with epitaxial extension layers and methods of forming the same
    43.
    发明申请
    Fin field effect transistors with epitaxial extension layers and methods of forming the same 审中-公开
    具有外延延伸层的鳍式场效应晶体管及其形成方法

    公开(公告)号：US20050199948A1

    公开(公告)日：2005-09-15

    申请号：US11074516

    申请日：2005-03-08

    申请人： Jong-Wook Lee ,  Deok-Hyung Lee

    发明人： Jong-Wook Lee ,  Deok-Hyung Lee

    IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/76 ,  H01L29/786

    CPC分类号： H01L29/7851 ,  H01L29/41791 ,  H01L2029/7858

    摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped semiconductor active region vertically protruding from a substrate and a gate structure on an upper surface and sidewalls of the fin-shaped semiconductor active region at a first portion thereof. The FinFET further includes a semiconductor epitaxial extension layer on the upper surface and sidewalls of the fin-shaped semiconductor active region at second portions thereof on opposite sides of the gate structure. The semiconductor epitaxial extension layer has a width that is greater than a width of the fin-shaped semiconductor active region at the first portion thereof. Related methods are also discussed.

    摘要翻译： 翅片场效应晶体管（FinFET）器件包括从基板垂直突出的鳍状半导体有源区和其上表面上的栅极结构以及鳍状半导体有源区的第一部分的侧壁。 FinFET还在栅极结构的相对侧上的第二部分处包括在半导体有源区的上表面上的半导体外延延伸层和鳍状半导体有源区的侧壁。 半导体外延延伸层的宽度大于其第一部分的鳍状半导体有源区的宽度。 还讨论了相关方法。

    Vertical-type non-volatile memory devices and methods of manufacturing the same
    44.
    发明授权
    Vertical-type non-volatile memory devices and methods of manufacturing the same 有权
    垂直型非易失性存储器件及其制造方法

    公开(公告)号：US08236650B2

    公开(公告)日：2012-08-07

    申请号：US12686065

    申请日：2010-01-12

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

    摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘 渠道。

    Methods of manufacturing semiconductor devices including a doped silicon layer
    46.
    发明授权
    Methods of manufacturing semiconductor devices including a doped silicon layer 有权
    制造包括掺杂硅层的半导体器件的方法

    公开(公告)号：US08048784B2

    公开(公告)日：2011-11-01

    申请号：US12284565

    申请日：2008-09-23

    申请人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L21/36

    CPC分类号： H01L21/02532 ,  H01L21/02636 ,  H01L21/02675

    摘要： Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成含有硅材料的晶种层。 在种子层上形成含有非晶硅材料的非晶硅层。 非晶硅层掺杂有杂质。 将激光束照射到非晶硅层上以产生非晶硅层的相变，并且基于种子层将非晶硅层改变为单晶硅层。

    VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    47.
    发明申请
    VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直型非挥发性记忆体装置及其制造方法

    公开(公告)号：US20100112769A1

    公开(公告)日：2010-05-06

    申请号：US12686065

    申请日：2010-01-12

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

    摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘 渠道。

    Vertical type semiconductor device
    48.
    发明申请
    Vertical type semiconductor device 有权
    垂直型半导体器件

    公开(公告)号：US20100109079A1

    公开(公告)日：2010-05-06

    申请号：US12588948

    申请日：2009-11-03

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7827 ,  H01L29/66666

    摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

    摘要翻译： 垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。 衬底可分为有源区和隔离层。 可以在对应于有源区的衬底中形成第一杂质区。 通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。 第二杂质区可以形成在沟道图案组的上部。 栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。 栅极绝缘层图案可以与沟道图案组的上表面间隔开。 栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

    Vertical semiconductor device, dram device including the same
    49.
    发明申请
    Vertical semiconductor device, dram device including the same 审中-公开
    垂直半导体器件，包括相同的电容器件

    公开(公告)号：US20100078698A1

    公开(公告)日：2010-04-01

    申请号：US12585776

    申请日：2009-09-24

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L27/06 ,  H01L29/78

    CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

    摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

    摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。