Abstract:
Lower electrodes of capacitors composed of a texturizing underlayer and a conductive material overlayer are provided. The lower electrodes have an upper roughened surface. In one embodiment, the texturizing layer is composed of porous or relief nanostructures comprising a polymeric material, for example, silicon oxycarbide. In another embodiment, the texturizing underlayer is in the form of surface dislocations composed of annealed first and second conductive metal layers, and the conductive metal overlayer is agglomerated onto the surface dislocations as nanostructures in the form of island clusters.
Abstract:
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.
Abstract:
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In a first embodiment of the present invention, a semiconductor structure is placed into a first treatment vessel and chemically treated. Following the chemical treatment, the semiconductor structure is transferred directly to a second treatment vessel where it is rinsed with DI water and then dried. The second treatment vessel is flooded with both DI water and a gas that is inert to the ambient, such as nitrogen, to form a DI water bath upon which an inert atmosphere is maintained during rinsing. Next, an inert gas carrier laden with IPA vapor is fed into the second treatment vessel. After sufficient time, a layer of IPA has formed upon the surface of the DI water bath to form an IPA-DI water interface. The semiconductor structure is drawn out of the DI water bath at a rate that allows substantially all DI water, and contaminants therein, to be entrained beneath the IPA-DI water interface. In a second embodiment of the present invention, chemical treatment, rinsing, and drying are carried out in a single vessel. In a third embodiment of the present invention, a retrofit spray/dump rinser with a lid is used for rinsing and drying according to the method of the present invention.
Abstract:
A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of a fluorine source, a non-aqueous solvent, a complementary acid, and a surface passivation agent. The fluorine source is typically hydrofluoric acid. The non-aqueous solvent is typically a polyhydric alcohol such as propylene glycol. The complementary acid is typically either phosphoric acid or hydrochloric acid. The surface passivation agent is typically a carboxylic acid such as citric acid. Exposing the substrate to the conditioning solution removes the remaining dry etch residues while minimizing removal of material from desired substrate features.
Abstract:
A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.
Abstract:
A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.
Abstract:
Compositions of ammonium fluoride, propylene glycol, and water and methods of using these compositions to remove etch residues from silicon substrates which result from plasma or reactive ion etching of silicon substrate are provided. Not only do the compositions of the present invention overcome the environmental concerns associated with the use of ethylene glycol, but unlike previous compositions of ammonium fluoride in propylene glycol which are acidic, the compositions of the present invention are neutral to slightly basic (i.e., pH 7 to about pH 8). Hence, they remove etch residues from silicon substrates with minimal attack on other features on the silicon substrates.
Abstract:
A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.
Abstract:
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
Abstract:
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.