摘要:
A scanning probe microscope operates in the manner of an atomic force microscope during intermittent periods of scanning motion, in which a sample surface is driven so that a scan line on the surface is moved past a probe tip being vibrated in engagement with the surface. Between these intermittent periods of scanning motion, the vibrating probe tip is moved out of engagement with the sample surface, so that the amplitude and phase shift of probe tip vibrations are determined by the gradient of a force field extending outward from the sample surface. Such a force field is established when the probe tip is attracted by, or repelled from, a magnetic or electric field at or near the sample surface. For each sample point, the system stores data representing the height of the sample surface and the force field.
摘要:
The vibrating probe of a scanning force microscope is brought into engagement with a sample surface in an initial approach process moving the probe toward the sample surface until the amplitude of probe vibration at an excitation frequency is measurably affected by forces between the tip and the sample, and then in a final approach process in which a change in vibration amplitude caused by a dithering vibration superimposed on the excitation vibration exceeds a pre-determined threshold limit. The excitation frequency is reduced if the phase angle of vibrations exceeds another limit, and the amplitude of the excitation driving function is increased as the amplitude or tip vibration falls below a setpoint. During approach and scanning, vibration amplitude is measured through a demodulator having an intermediate reference signal locked in phase with the tip motion signal.
摘要:
According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要:
Side illumination is combined with scanning interferometry to provide a means for measuring with a single data-acquisition scan surfaces that contain sections suitable for interferometric processing as well as sections that are not suitable because of lack of fringes produced by the measurement. In the sections where no fringes are produced, the irradiance detected during the scan is processed using a depth-from-focus mapping method to yield a corresponding measurement. The result is a complete profilometric measurement of the sample surface with a single scan. In addition, by increasing sample irradiance through side illumination, the structural features of the sample become markedly more visible than when illuminated only by the object beam of the interferometer, which greatly facilitates finding focus and identifying regions of interest for the measurement.
摘要:
In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
摘要:
A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译:具有100 petaOPS规模计算的多Petascale高效并行超级计算机,其成本,功耗和占地面积都在降低,并且允许从互连角度来看处理节点的最大封装密度。 超级计算机利用了VLSI的技术进步,实现了许多处理器可以集成到单个专用集成电路(ASIC)中的计算模型。 每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC,每个处理器具有对所有系统资源的完全访问,并且使得处理器能够对诸如计算或消息传递I / O 并且优选地,根据应用内的各种算法阶段实现功能的自适应分割,或者如果I / O或其他处理器未被充分利用,则可以参与计算或通信节点通过五维环面网络互连 使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。
摘要:
According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要:
According to embodiments of the invention, an in-cell capacitive contact panel and a manufacturing method thereof are provided. The in-cell capacitive touch panel comprises an array substrate. The array substrate comprises a display pixel structure and a touch circuit, and the touch circuit comprises a sensing unit and an amplifying unit connected with each other. The sensing unit is connected to a gate line in the display pixel structure. A switch-on voltage is provided by the gate line in the display pixel structure to the sensing unit, a voltage is generated in the sensing unit after the sensing unit is switched on, the voltage generated in the sensing unit is changed by a touch operation, the amplifying unit amplifies the voltage change in the sensing unit and outputs the amplified voltage change.
摘要:
Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.
摘要:
A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.