公开(公告)号：US07077903B2

公开(公告)日：2006-07-18

申请号：US10705577

申请日：2003-11-10

申请人： Katherina E. Babich ,  Scott D. Halle ,  David V. Horak ,  Arpan P. Mahorowala ,  Wesley C. Natzle ,  Dirk Pfeiffer ,  Hongwen Yan

发明人： Katherina E. Babich ,  Scott D. Halle ,  David V. Horak ,  Arpan P. Mahorowala ,  Wesley C. Natzle ,  Dirk Pfeiffer ,  Hongwen Yan

IPC分类号： C30B25/02

CPC分类号： H01L21/0275 ,  H01L21/31144 ,  H01L21/32139 ,  Y10T428/24843

摘要： Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA layer (used as an ARC and/or hardmask) with etch selectivity to the patterned photoresist, and etching to pattern transfer through a dielectric layer of nitride. This is accomplished by oxidizing a TERA layer after etching pattern transfer through the TERA layer to form an oxidized TERA layer having chemical properties similar to oxide. The methods provide all of the advantages of the TERA material and allows for high etch selectivity (approximately 5–10:1) for etching to pattern transfer through nitride. In addition, the methodology reduces LER and allows for trimming despite reduced photoresist thickness.

摘要翻译： 公开了产生纳米结构和提高蚀刻选择性的方法，以及纳米结构。 本发明实现了可调谐抗蚀抗反射（TERA）材料集成方案，其对蚀刻图案转移通过TERA层（用作ARC和/或硬掩模）提供了高蚀刻选择性，具有对图案化光致抗蚀剂的蚀刻选择性，以及 蚀刻到通过氮化物的介电层的图案转移。 这是通过在通过TERA层蚀刻图案转移之后氧化TERA层来实现的，以形成具有与氧化物相似的化学性质的氧化TERA层。 这些方法提供了TERA材料的所有优点，并且允许高蚀刻选择性（约5-10:1）蚀刻到通过氮化物的图案转移。 此外，该方法减少LER，并允许尽管减少光致抗蚀剂厚度的修剪。

公开(公告)号：US20050260819A1

公开(公告)日：2005-11-24

申请号：US10709652

申请日：2004-05-20

申请人： Michael Belyansky ,  Joyce Liu ,  Hsing Jen Wann ,  Richard Wise ,  Hongwen Yan

发明人： Michael Belyansky ,  Joyce Liu ,  Hsing Jen Wann ,  Richard Wise ,  Hongwen Yan

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.

摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。 栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。 降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。 优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。 间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。 间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。 可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

公开(公告)号：US06541320B2

公开(公告)日：2003-04-01

申请号：US09928210

申请日：2001-08-10

申请人： Jeffrey Brown ,  Richard Wise ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

发明人： Jeffrey Brown ,  Richard Wise ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

IPC分类号： H01L21336

CPC分类号： H01L21/32137 ,  H01L21/28114 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/42376

摘要： A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.

摘要翻译： 一种用于形成在栅极介电层上具有栅极导体层的缺口栅极结构的方法和结构。 栅极导体层具有第一厚度。 本发明的方法包括在栅极导体层上图案化掩模，在未被掩模保护的区域中将栅极导体层蚀刻到减小的厚度（减小的厚度小于第一厚度），在栅极导体上沉积钝化膜 蚀刻钝化膜以从栅极导体层的水平部分去除钝化膜（使用各向异性蚀刻），选择性地蚀刻栅极导体层以从不受掩模或钝化膜保护的所有区域去除栅极导体层 。 这在栅极导体与栅极介电层相遇的拐角处形成栅极导体层内的底切凹口。 钝化膜包括含C的膜，含Si膜，含Si-C的膜或其组合。

公开(公告)号：US08673737B2

公开(公告)日：2014-03-18

申请号：US13274389

申请日：2011-10-17

申请人： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

发明人： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

IPC分类号： H01L21/76

CPC分类号： H01L29/423 ,  H01L21/762 ,  H01L27/10805 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

摘要翻译： 提供了一种用于eDRAM的阵列或护城隔离结构及其制造方法。 该方法包括形成用于存储器阵列的深沟槽和隔离区域。 该方法包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。 该方法包括用金属填充用于存储器阵列的深沟槽的剩余部分，并用金属衬里隔离区域的深沟槽。 该方法包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区域的深沟槽的剩余部分。 该方法包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。 存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

公开(公告)号：US20120256278A1

公开(公告)日：2012-10-11

申请号：US13080084

申请日：2011-04-05

申请人： Ying Zhang ,  Qingyun Yang ,  Hongwen Yan

发明人： Ying Zhang ,  Qingyun Yang ,  Hongwen Yan

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.

摘要翻译： 一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。 高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。 半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。

公开(公告)号：US08227874B2

公开(公告)日：2012-07-24

申请号：US12861913

申请日：2010-08-24

申请人： James William Adkisson ,  Michael Patrick Chudzik ,  Jeffrey Peter Gambino ,  Hongwen Yan

发明人： James William Adkisson ,  Michael Patrick Chudzik ,  Jeffrey Peter Gambino ,  Hongwen Yan

IPC分类号： H01L29/78

CPC分类号： H01L29/1037 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.

摘要翻译： 半导体结构。 半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和 （v）第一栅介质角区域。 最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。 第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii） ）不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

公开(公告)号：US08018005B2

公开(公告)日：2011-09-13

申请号：US12823225

申请日：2010-06-25

申请人： Bruce Bennett Doris ,  William K. Henson ,  Richard Stephen Wise ,  Hongwen Yan

发明人： Bruce Bennett Doris ,  William K. Henson ,  Richard Stephen Wise ,  Hongwen Yan

IPC分类号： H01L21/70

CPC分类号： H01L21/823842

摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.

摘要翻译： 半导体结构。 半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向 并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

公开(公告)号：US07863124B2

公开(公告)日：2011-01-04

申请号：US11746759

申请日：2007-05-10

申请人： Michael Chudzik ,  Bruce B. Doris ,  William K. Henson ,  Hongwen Yan ,  Ying Zhang

发明人： Michael Chudzik ,  Bruce B. Doris ,  William K. Henson ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different nFET and pFET gate electrode materials.

摘要翻译： 形成微电子结构的方法使用位于目标层上的掩模层。 可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。 可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。 可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。 该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的nFET和pFET栅电极材料。

公开(公告)号：US07820555B2

公开(公告)日：2010-10-26

申请号：US11870577

申请日：2007-10-11

申请人： Bruce B. Doris ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Bruce B. Doris ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28088 ,  H01L21/32136 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/51

摘要： A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.

摘要翻译： 形成用于互补金属氧化物半导体（CMOS）器件的图案化多层金属栅极结构的方法包括执行第一蚀刻工艺以去除包括在栅极堆叠内的多晶硅层的暴露部分，形成在也包括在栅极堆叠内的金属层上的多晶硅层 门堆 在第一蚀刻工艺之后氧化暴露的金属层的顶部部分，以便产生相对于多晶硅层具有蚀刻选择性的金属氧化物层; 通过物理离子轰击的组合除去金属氧化物层，并向其中引入各向同性化学成分，以防止多晶硅层底角的氧化物质; 以及执行第二蚀刻工艺以去除所述金属层的暴露部分。

公开(公告)号：US20100112800A1

公开(公告)日：2010-05-06

申请号：US12683535

申请日：2010-01-07

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/28

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。