公开(公告)号：US10269405B2

公开(公告)日：2019-04-23

申请号：US15605508

申请日：2017-05-25

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G06F12/0804

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US10199574B2

公开(公告)日：2019-02-05

申请号：US15941153

申请日：2018-03-30

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L27/108 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

公开(公告)号：US10146601B2

公开(公告)日：2018-12-04

申请号：US14297386

申请日：2014-06-05

Applicant: Everspin Technologies, Inc.

Inventor： Jon Slaughter ,  Dimitri Houssameddine ,  Thomas Andre ,  Syed M. Alam

IPC: G06F11/00 ,  G06F11/07 ,  G11C11/16

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

公开(公告)号：US20180182443A1

公开(公告)日：2018-06-28

申请号：US15851816

申请日：2017-12-22

Applicant: Everspin Technologies, Inc.

Inventor： Han-Jong Chia ,  Sumio Ikegawa ,  Michael Tran ,  Jon Slaughter

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01L43/12

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/5607 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.

公开(公告)号：US20180130944A1

公开(公告)日：2018-05-10

申请号：US15860914

申请日：2018-01-03

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu Whig ,  Phillip Mather ,  Kenneth Smith ,  Sanjeev Aggarwal ,  Jon Slaughter ,  Nicholas Rizzo

IPC: H01L43/12 ,  G01R33/00 ,  G01R33/09 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US09881695B2

公开(公告)日：2018-01-30

申请号：US15356223

申请日：2016-11-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US20170125670A1

公开(公告)日：2017-05-04

申请号：US15400889

申请日：2017-01-06

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

公开(公告)号：US09525129B2

公开(公告)日：2016-12-20

申请号：US15142721

申请日：2016-04-29

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu Whig ,  Phillip Mather ,  Kenneth Smith ,  Sanjeev Aggarwal ,  Jon Slaughter ,  Nicholas Rizzo

IPC: H01L43/12 ,  H01L27/22 ,  G01R33/02 ,  B82Y25/00 ,  G01R33/00 ,  G01R33/09 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US09444037B2

公开(公告)日：2016-09-13

申请号：US15043633

申请日：2016-02-15

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: A magnetoresistive memory array including a plurality of magnetoresistive memory elements wherein each magnetoresistive memory element comprises a free layer including at least one ferromagnetic layer having perpendicular magnetic anisotropy, a fixed layer, and a tunnel barrier, disposed between and in contact with the free and fixed layers. The tunnel barrier includes a first metal-oxide layer, having a thickness between 1 and 10 Angstroms, a second metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed on the first metal-oxide layer, and a third metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed over the second metal-oxide layer. In one embodiment, the third metal-oxide layer is in contact with the free layer or fixed layer. The tunnel barrier may also include a fourth metal-oxide layer, having a thickness between 1 and 10 Angstroms, disposed between the second and third metal-oxide layers.

Abstract translation: 一种包括多个磁阻存储元件的磁阻存储器阵列，其中每个磁阻存储元件包括自由层，该自由层包括至少一个具有垂直磁各向异性的铁磁层，固定层和隧道势垒，该自由层设置在自由和固定 层。 隧道势垒包括设置在第一金属氧化物层上的第一金属氧化物层，其厚度为1至10埃，厚度为3埃至6埃的第二金属氧化物层，以及第三金属氧化物层， 氧化物层，其厚度为3埃至6埃，设置在第二金属氧化物层上。 在一个实施例中，第三金属氧化物层与自由层或固定层接触。 隧道势垒还可以包括设置在第二和第三金属氧化物层之间的厚度在1埃和10埃之间的第四金属氧化物层。

公开(公告)号：US20160163964A1

公开(公告)日：2016-06-09

申请号：US15046483

申请日：2016-02-18

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract translation: 磁阻存储元件（例如，自旋转矩磁阻存储元件）包括固定磁性层，具有垂直磁各向异性的自由磁性层和设置在固定磁性层和自由磁性层之间的第一电介质。 第一电介质的第一表面与自由磁性层的第一表面接触。 磁阻存储元件还包括第二电介质，其具有与自由磁性层的第二表面接触的第一表面，包括导电材料的导体以及设置在第二电介质和导体之间的电极。 电极包括：（i）具有与第二电介质的第二表面接触的表面的非铁磁部分，和（ii）第二部分，其包括设置在第二电介质的非铁磁部分之间的至少一个铁磁材料 电极和导体。