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265 条记录 (耗时 0.036 秒)

    Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode
    41.
    发明授权
    Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
    一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极

    公开(公告)号：US06861350B1

    公开(公告)日：2005-03-01

    申请号：US10464508

    申请日：2003-06-19

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H10L21/4763 ,  H10L21/44

    CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

    摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

    摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

    Method for semiconductor wafer planarization by CMP stop layer formation
    44.
    发明授权
    Method for semiconductor wafer planarization by CMP stop layer formation 失效
    通过CMP停止层形成的半导体晶片平面化方法

    公开(公告)号：US06770523B1

    公开(公告)日：2004-08-03

    申请号：US10190397

    申请日：2002-07-02

    申请人： Kashmir S. Sahota ,  Jeffrey P. Erhardt ,  Arvind Halliyal ,  Minh Van Ngo ,  Krishnashree Achuthan

    发明人： Kashmir S. Sahota ,  Jeffrey P. Erhardt ,  Arvind Halliyal ,  Minh Van Ngo ,  Krishnashree Achuthan

    IPC分类号： H01L218238

    CPC分类号： H01L21/76229 ,  H01L21/31053

    摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

    摘要翻译： 提供了具有半导体晶片的集成电路的制造方法。 化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。 化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。 在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。 然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。 然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
    45.
    发明授权
    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
    具有高K电介质的半导体器件具有渐变介电常数的间隔物

    公开(公告)号：US06764966B1

    公开(公告)日：2004-07-20

    申请号：US10085278

    申请日：2002-02-27

    申请人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    发明人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    IPC分类号： H01L2128

    CPC分类号： H01L29/6656 ,  H01L29/66833 ,  H01L29/78

    摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

    摘要翻译： 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

    Doped copper interconnects using laser thermal annealing
    46.
    发明授权
    Doped copper interconnects using laser thermal annealing 失效
    使用激光热退火的掺杂铜互连

    公开(公告)号：US06731006B1

    公开(公告)日：2004-05-04

    申请号：US10323941

    申请日：2002-12-20

    申请人： Arvind Halliyal ,  Minh Van Ngo

    发明人： Arvind Halliyal ,  Minh Van Ngo

    IPC分类号： H01L2348

    CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.

    摘要翻译： 半导体器件及其制造方法包括第一金属化层，第一蚀刻停止层，电介质层和延伸穿过介电层和第一蚀刻停止层的开口。 第一蚀刻停止层设置在第一金属化层上。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 将掺杂剂引入金属中并通过激光热退火来激活。 在第二金属特征附近的第二金属特征的下部中的金属内的掺杂剂的浓度大于第二金属特征的中心部分中的掺杂剂的浓度，并且金属中掺杂剂的浓度在 第二金属特征的上部大于第二金属特征的中心部分中的掺杂剂的浓度。

    Method of forming reliable Cu interconnects
    47.
    发明授权
    Method of forming reliable Cu interconnects 失效
    形成可靠的Cu互连的方法

    公开(公告)号：US06727176B2

    公开(公告)日：2004-04-27

    申请号：US09986267

    申请日：2001-11-08

    申请人： Minh Van Ngo ,  Arvind Halliyal ,  Eric Paton

    发明人： Minh Van Ngo ,  Arvind Halliyal ,  Eric Paton

    IPC分类号： H01L2144

    CPC分类号： H01L21/76882

    摘要： Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

    摘要翻译： 通过用Cu填充电介质层中的开口，然后在NH 3中激光热退火以形成可靠的Cu互连，以减少氧化铜和回流沉积的Cu，从而消除空隙并降低接触电阻。 实施例包括使用约200至约2,000sccn的NH 3流速的激光热退火。

    Method of forming reliable capped copper interconnects
    48.
    发明授权
    Method of forming reliable capped copper interconnects 有权
    形成可靠封盖铜互连的方法

    公开(公告)号：US06660634B1

    公开(公告)日：2003-12-09

    申请号：US10291612

    申请日：2002-11-12

    申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

    发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

    IPC分类号： H01L2144

    CPC分类号： H01L21/76862 ,  H01L21/76801 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/902 ,  Y10S438/906 ,  H01L2924/00

    摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

    摘要翻译： 扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附通过处理Cu或Cu合金互连构件的暴露表面而显着增强：（a）在等离子体条件下用氨和硅烷或二氯硅烷形成铜 硅化物层; 或（b）与氨等离子体接触，然后与硅烷或二氯硅烷反应，在其上形成硅化铜层。 然后将扩散阻挡层沉积在硅化铜层上。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，然后处理Cu / Cu合金互连的暴露表面以在其上形成硅化铜层，并沉积氮化硅 扩散阻挡层在硅化铜层上。

    Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation
    49.
    发明授权
    Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation 失效
    在具有从气体前体沉积的硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗

    公开(公告)号：US06660621B1

    公开(公告)日：2003-12-09

    申请号：US10163461

    申请日：2002-06-07

    申请人： Paul R. Besser ,  Minh Van Ngo

    发明人： Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L213205

    CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/665

    摘要： A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.

    摘要翻译： 在半导体晶片中形成超浅结的方法形成栅极和源极/漏极结，其在栅极和源极/漏极结上的第一金属硅化物区具有上表面。 这些第一金属硅化物区域具有较高的电阻率。 通过等离子体增强化学气相沉积（PECVD）将非晶硅沉积在第一金属硅化物区域上。 PECVD工艺可以是较低压力的沉积工艺，在多个工位上执行以在多层中形成非晶硅层。 这就形成了跨越晶片的更均匀的非晶硅层和不同的图案化密度，从而提高了器件性能和特性。 然后通过第一金属硅化物区域和通过PECVD工艺沉积的非晶硅的扩散反应，进行退火以形成较低电阻率的第二金属硅化物区域。