公开(公告)号：US20190252522A1

公开(公告)日：2019-08-15

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/306 ,  H01L21/285

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

公开(公告)号：US20190148149A1

公开(公告)日：2019-05-16

申请号：US15810638

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L21/20 ,  H01L29/10 ,  H01L29/78 ,  H01L21/263 ,  C23C14/58 ,  H01L21/02

Abstract: A method of forming a crystalline semiconductor material on the basis of a very thin semiconductor base material and an amorphous semiconductor material deposited thereon is disclosed. Radiation-based anneal process techniques may be applied by using appropriate radiation wavelengths, for instance, below 380 nm, in order to efficiently restrict energy deposition to the surface-near area. A solid and crystalline bottom portion of the semiconductor base material may be reliably preserved, thereby achieving crystallization of the overlying material portions and, in particular, of the previously deposited amorphous semiconductor material. Extremely thin channel regions of fully depleted SOI transistor elements may be used as a semiconductor base material, upon which raised drain and source regions may be formed in a later manufacturing stage, thereby substantially avoiding any process irregularities, which are conventionally associated with the epitaxial growth of a semiconductor material on a very thin semiconductor base material.

公开(公告)号：US10283365B1

公开(公告)日：2019-05-07

申请号：US15810638

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L21/20 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L21/263 ,  C23C14/58

Abstract: A method of forming a crystalline semiconductor material on the basis of a very thin semiconductor base material and an amorphous semiconductor material deposited thereon is disclosed. Radiation-based anneal process techniques may be applied by using appropriate radiation wavelengths, for instance, below 380 nm, in order to efficiently restrict energy deposition to the surface-near area. A solid and crystalline bottom portion of the semiconductor base material may be reliably preserved, thereby achieving crystallization of the overlying material portions and, in particular, of the previously deposited amorphous semiconductor material. Extremely thin channel regions of fully depleted SOI transistor elements may be used as a semiconductor base material, upon which raised drain and source regions may be formed in a later manufacturing stage, thereby substantially avoiding any process irregularities, which are conventionally associated with the epitaxial growth of a semiconductor material on a very thin semiconductor base material.

公开(公告)号：US20190035815A1

公开(公告)日：2019-01-31

申请号：US15664061

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/266

CPC classification number: H01L27/1207 ,  H01L21/266 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/84

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

公开(公告)号：US10157996B2

公开(公告)日：2018-12-18

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

公开(公告)号：US09953876B1

公开(公告)日：2018-04-24

申请号：US15282211

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Hans-Juergen Thees

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0883 ,  H01L29/786

Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

公开(公告)号：US09793372B1

公开(公告)日：2017-10-17

申请号：US15163806

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.

公开(公告)号：US20170288015A1

公开(公告)日：2017-10-05

申请号：US15457384

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Steffen Sichler

IPC: H01L29/06 ,  H01L23/535 ,  H01L29/49 ,  H01L29/08 ,  H01L27/12 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

公开(公告)号：US20170040354A1

公开(公告)日：2017-02-09

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract translation: 根据一些示例性实施例，本公开提供包括形成在半导体衬底中的有源区的电容器结构，包括形成在有源区中的源区和漏区以及形成在有源区上方的栅极的MOSFET器件，以及 第一电极和形成在MOSFET器件上方的金属化层中的第二电极，其中第一电极经由相应的源极和漏极触点与源极和漏极区域电连接，并且第二电极经由栅极触点与栅电极电连接 。

公开(公告)号：US09514942B1

公开(公告)日：2016-12-06

申请号：US15060009

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Thorsten Kammler ,  Andreas Hellmich ,  Carsten Grass

IPC: H01L21/28 ,  H01L21/66 ,  H01L21/311 ,  H01L21/32 ,  H01L27/12

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L22/26 ,  H01L27/1207

Abstract: A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Abstract translation: 公开了一种在具有体积区域和SOI区域的形貌的混合衬底结构上形成栅极结构的方法，包括在SOI和体区上形成栅极材料层，在栅极材料层上方形成掩模层，形成第一 在所述掩模层上方形成平坦化层，在所述第一平坦化层上方形成第一栅极结构掩模图案，使与所述第一栅极结构掩模图案对准的所述第一平坦化图案图案化，以及根据所述图案化的第一平坦化层图案化所述掩模层， 在栅极掩模上设置在栅极材料层上方。