公开(公告)号：US20180182757A1

公开(公告)日：2018-06-28

申请号：US15862064

申请日：2018-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Murat Kerem Akarvardar ,  Lars Liebmann ,  Nigel Graeme Cave

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

公开(公告)号：US09881830B2

公开(公告)日：2018-01-30

申请号：US14590591

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L21/76202 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

公开(公告)号：US09601383B1

公开(公告)日：2017-03-21

申请号：US14941885

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar

IPC: H01L21/337 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/088 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/785

Abstract: A semiconductor structure for a FinFET in fabrication is provided, the structure including a bulk semiconductor substrate initially with a hard mask over the substrate. Isolation trenches between regions of the structure where the fins will be are formed prior to the fins, and filled with selectively removable sacrificial isolation material. Remains of the hard mask are removed and another hard mask formed over the structure with filled isolation trenches. Fins are then formed throughout the structure, including the regions of sacrificial isolation material, which is thereafter selectively removed.

公开(公告)号：US09564486B2

公开(公告)日：2017-02-07

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US09455140B2

公开(公告)日：2016-09-27

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78 ,  H01L21/18

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。

公开(公告)号：US20160268399A1

公开(公告)日：2016-09-15

申请号：US14643409

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Steven Bentley

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract translation: 本文公开的一种说明性方法包括在器件的源极/漏极区域中形成绝缘材料层，其中绝缘材料层具有与栅极盖层的上表面基本上平面的上表面 使绝缘材料层凹陷，使得其凹陷的上表面暴露在鳍片的表面上，执行另一蚀刻工艺以移除鳍片的至少一部分，从而限定位于凹鳍片上方的凹陷散热片沟槽，并形成外延 所述半导体材料至少部分地位于所述凹陷散热片沟槽中。

公开(公告)号：US09425289B2

公开(公告)日：2016-08-23

申请号：US14471038

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L21/20 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/30604 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括在凹陷鳍结构上方的绝缘材料层中形成凹陷翅片结构和替换翅片空腔，在替换翅片腔中形成至少第一和第二独立的外延半导体材料层，其中每个 第一层和第二层具有不同浓度的锗，对第一层和第二层进行退火处理，以在翅片腔中形成基本上均匀的SiGe替换翅片，并且在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US09337022B1

公开(公告)日：2016-05-10

申请号：US14742471

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/304 ,  H01L29/165

CPC classification number: H01L21/0245 ,  H01L21/02496 ,  H01L21/0251 ,  H01L21/02551 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of creating a virtual relaxed substrate includes providing a bulk semiconductor substrate, and creating a layer of strained semiconductor material on the substrate, a non-zero lattice mismatch of less than about 2% being present between the substrate and the layer of strained semiconductor material, and the layer of strained semiconductor material having a thickness of from about 50 nm to about 150 nm. The method further includes etching through the layer of strained semiconductor material and into the substrate to create shaped pillars separated by slits and sized to achieve edge effect relaxation throughout each shaped pillar, merging a top portion of the pillars with single crystal growth of epitaxial material to create a continuous surface while substantially maintaining the slits, and creating a virtual relaxed substrate by creating a layer of epitaxial composite semiconductor material over the continuous surface.

Abstract translation: 创建虚拟松弛衬底的方法包括提供体半导体衬底，以及在衬底上产生应变半导体材料层，小于约2％的非零晶格失配存在于衬底和应变半导体层之间 材料和具有约50nm至约150nm厚度的应变半导体材料层。 该方法还包括蚀刻通过应变半导体材料层并进入衬底以产生由狭缝分开的成形柱，并且尺寸设计成实现每个成形柱的边缘效应松弛，将柱的顶部部分与外延材料的单晶生长合并成 创建连续的表面，同时基本上保持狭缝，并通过在连续表面上形成外延复合半导体材料层来产生虚拟的松弛衬底。

公开(公告)号：US20160064526A1

公开(公告)日：2016-03-03

申请号：US14471038

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/30604 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括在凹陷鳍结构上方的绝缘材料层中形成凹陷翅片结构和替换翅片空腔，在替换翅片腔中形成至少第一和第二独立的外延半导体材料层，其中每个 第一层和第二层具有不同浓度的锗，对第一层和第二层进行退火处理，以在翅片腔中形成基本上均匀的SiGe替换翅片，并且在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US09245980B2

公开(公告)日：2016-01-26

申请号：US14242472

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。