公开(公告)号：US08921904B2

公开(公告)日：2014-12-30

申请号：US14032567

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Peter Baars ,  Matthias Goldbach

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract translation: 提供了半导体器件和相关的制造方法。 示例性的制造方法包括形成一对栅极结构，其具有布置在该对的第一栅极结构和该对的第二栅极结构之间的介质区域，并且在第一栅极结构和第二栅极结构之间的介电区域中形成空隙区域 门结构。 第一和第二栅极结构各自包括第一栅极电极材料，其中该方法通过去除第一栅电极材料继续，以提供对应于栅极结构的第二和第三空隙区域，并在第一空隙区域中形成第二栅电极材料， 第二空隙区域和第三空隙区域。

公开(公告)号：US20140203339A1

公开(公告)日：2014-07-24

申请号：US14226176

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

Abstract translation: 半导体器件包括位于有源区上方的高k金属栅电极结构，具有位于栅极高度的顶表面，并且包括高k电介质材料和电极金属。 引出的漏极和源极区域横向邻近高k金属栅极电极结构定位并连接到有源区域，并且每个升高的漏极和源极区域的顶表面位于栅极下方的接触高度水平处 身高。 蚀刻停止层位于凸起的漏极和源极区域的顶表面上方，并且接触元件连接到凸起的漏极和源极区域之一，接触元件延伸穿过蚀刻停止层， k金属栅极电极结构和升高的漏极和源极区域。

公开(公告)号：US08742510B2

公开(公告)日：2014-06-03

申请号：US13718158

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

IPC: H01L21/70 ,  H01L21/02 ,  H01L23/48 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

公开(公告)号：US10707330B2

公开(公告)日：2020-07-07

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L21/285 ,  H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

公开(公告)号：US10522655B2

公开(公告)日：2019-12-31

申请号：US15711674

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20190043963A1

公开(公告)日：2019-02-07

申请号：US15667755

申请日：2017-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees ,  Clemens Fitz

IPC: H01L29/66 ,  H01L29/417

Abstract: A transistor element of a sophisticated semiconductor device includes a gate electrode structure including a metal-containing electrode material instead of the conventionally used highly doped semiconductor material. The metal-containing electrode material may be formed in an early manufacturing stage, thereby reducing overall complexity of patterning the gate electrode structure in approaches in which the gate electrode structure is formed prior to the formation of the drain and source regions. Due to the metal-containing electrode material, high conductivity at reduced parasitic capacitance may be achieved, thereby rendering the techniques of the present disclosure as highly suitable for further device scaling.

公开(公告)号：US10103067B1

公开(公告)日：2018-10-16

申请号：US15617388

申请日：2017-06-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Gunter Grasshoff ,  Rico Hueselitz

IPC: H01L21/76 ,  H01L21/84 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L21/8238

Abstract: A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a trench through the semiconductor layer and extending at least partially into the buried oxide layer, forming a liner at sidewalls of the trench, deepening the trench into the semiconductor bulk substrate, filling the deepened trench with a flowable dielectric material, and performing an anneal of the flowable dielectric material.

公开(公告)号：US20180047642A1

公开(公告)日：2018-02-15

申请号：US15232090

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/84 ,  H01L21/265 ,  H01L27/12 ,  H01L21/311

CPC classification number: H01L21/84 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/7834

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

公开(公告)号：US09608003B2

公开(公告)日：2017-03-28

申请号：US15193770

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/308 ,  H01L21/321 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

公开(公告)号：US09553030B2

公开(公告)日：2017-01-24

申请号：US14695232

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L21/845 ,  H01L27/127 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78684

Abstract: A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.

Abstract translation: 提供一种形成半导体器件的方法，包括：提供绝缘体上半导体（SOI）晶片，其包括第一半导体层，其包含第一材料成分并形成在掩埋氧化物（BOX）层上，并形成P 通道晶体管器件，包括只在第一半导体层的第一部分上形成第二半导体层，其中第二半导体层包括第一材料成分和与第一材料成分不同的第二材料成分，在第一 半导体层，然后进行热退火，以将第二材料成分从第二半导体层推入第一半导体层。