公开(公告)号：US08738167B2

公开(公告)日：2014-05-27

申请号：US13398481

申请日：2012-02-16

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： G06F19/00 ,  H01L21/30 ,  H01L21/46 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

公开(公告)号：US08629553B2

公开(公告)日：2014-01-14

申请号：US13398505

申请日：2012-02-16

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L23/34 ,  H01L21/30

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US08350269B2

公开(公告)日：2013-01-08

申请号：US13455174

申请日：2012-04-25

申请人： Subramanian S. Iyer ,  Edward J. Nowak

发明人： Subramanian S. Iyer ,  Edward J. Nowak

IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L27/12 ,  H01L27/088

CPC分类号： H01L21/76248 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/845 ,  H01L27/0886

摘要： Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., single-fin or multi-fin MUGFET, multiple series-connected single-fin, multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections). Also disclosed is a SOI structure formed using the above-described method.

摘要翻译： 公开了一种在体半导体起始晶片上形成绝缘体上半导体（SOI）结构的方法。 在晶片的顶表面上形成平行的半导体本体。 绝缘体层被沉积并凹进。 将半导体本体的暴露的上部用作种子材料，用于在绝缘体层上横向生长半导体材料的外延层，从而形成半导体层。 该半导体层可以用于形成一个或多个SOI器件（例如，单翅片或多翅片MUGFET，多个串联连接的单翅片，多翅片MUGFET）。 然而，SOI器件部件在半导体层的部分和/或部分上的放置应该是预先确定的，以避免可能影响器件性能的位置（例如，可以预先规定半导体层形成的半导体鳍片上的任何FET栅极的放置，以避免 连接的外延半导体材料部分之间的界面）。 还公开了使用上述方法形成的SOI结构。

公开(公告)号：US20120326309A1

公开(公告)日：2012-12-27

申请号：US13167107

申请日：2011-06-23

申请人： PAUL S ANDRY ,  Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser ,  Cornelia K. Tsang ,  Richard P. Volant

发明人： PAUL S ANDRY ,  Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser ,  Cornelia K. Tsang ,  Richard P. Volant

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

摘要翻译： 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

公开(公告)号：US20120205742A1

公开(公告)日：2012-08-16

申请号：US13455174

申请日：2012-04-25

申请人： Subramanian S. Iyer ,  Edward J. Nowak

发明人： Subramanian S. Iyer ,  Edward J. Nowak

IPC分类号： H01L27/12

CPC分类号： H01L21/76248 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/845 ,  H01L27/0886

摘要： Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., single-fin or multi-fin MUGFET, multiple series-connected single-fin, multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections). Also disclosed is a SOI structure formed using the above-described method.

摘要翻译： 公开了一种在体半导体起始晶片上形成绝缘体上半导体（SOI）结构的方法。 在晶片的顶表面上形成平行的半导体本体。 绝缘体层被沉积并凹进。 将半导体本体的暴露的上部用作种子材料，用于在绝缘体层上横向生长半导体材料的外延层，从而形成半导体层。 该半导体层可以用于形成一个或多个SOI器件（例如，单翅片或多翅片MUGFET，多个串联连接的单翅片，多翅片MUGFET）。 然而，SOI器件部件在半导体层的部分和/或部分上的放置应该是预先确定的，以避免可能影响器件性能的位置（例如，可以预先规定半导体层形成的半导体鳍片上的任何FET栅极的放置，以避免 连接的外延半导体材料部分之间的界面）。 还公开了使用上述方法形成的SOI结构。

公开(公告)号：US08227304B2

公开(公告)日：2012-07-24

申请号：US12710380

申请日：2010-02-23

申请人： Subramanian S. Iyer ,  Edward J. Nowak

发明人： Subramanian S. Iyer ,  Edward J. Nowak

IPC分类号： H01L21/84 ,  H01L21/20 ,  H01L27/12

CPC分类号： H01L21/76248 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/845 ,  H01L27/0886

摘要： Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on a bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., a single-fin or multi-fin MUGFET or multiple series-connected single-fin or multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections). Also disclosed is a SOI structure formed using the above-described method.

摘要翻译： 公开了一种在体半导体起始晶片上形成绝缘体上半导体（SOI）结构的方法。 在晶片的顶表面上形成平行的半导体本体。 绝缘体层被沉积并凹进。 将半导体本体的暴露的上部用作种子材料，用于在绝缘体层上横向生长半导体材料的外延层，从而形成半导体层。 该半导体层可用于形成一个或多个SOI器件（例如，单翅片或多翅片MUGFET或多个串联连接的单翅片或多翅片MUGFET）。 然而，SOI器件部件在半导体层的部分和/或部分上的放置应该是预先确定的，以避免可能影响器件性能的位置（例如，可以预先规定半导体层形成的半导体鳍片上的任何FET栅极的放置，以避免 连接的外延半导体材料部分之间的界面）。 还公开了使用上述方法形成的SOI结构。

公开(公告)号：US20110193193A1

公开(公告)日：2011-08-11

申请号：US12704084

申请日：2010-02-11

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US07982285B2

公开(公告)日：2011-07-19

申请号：US11970750

申请日：2008-01-08

申请人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

发明人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/52

CPC分类号： H01L23/5252 ,  G11C17/165 ,  G11C2229/763 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/928 ,  H01L2924/00

摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

摘要翻译： 本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的电介质层，其中一个或两个导体用作传统的反熔丝导体和 作为用于在编程期间直接加热反熔丝介电层的加热元件。

公开(公告)号：US20100314711A1

公开(公告)日：2010-12-16

申请号：US12194211

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L27/12 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。 提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。 第一有源电路层晶片比另一个晶片低成本。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US20100214995A1

公开(公告)日：2010-08-26

申请号：US12392188

申请日：2009-02-25

申请人： Subramanian S. Iyer ,  Christopher R. Cushing ,  Ajakumar R. Idnani ,  David R. Maas ,  J. Chris Stanaway

发明人： Subramanian S. Iyer ,  Christopher R. Cushing ,  Ajakumar R. Idnani ,  David R. Maas ,  J. Chris Stanaway

IPC分类号： H04W72/12

CPC分类号： H04W48/12 ,  H04W84/18

摘要： An apparatus and method for communicating system information in a wireless communication network. A first step 200 includes defining unicast threshold parameter(s). A next step 201 includes receiving a request for system information. A next step 202, 204 includes determining if the system information exceeds the threshold parameter(s). A next step 206-216 includes scheduling an ad-hoc broadcast of the system information if the system information exceeds the threshold parameter(s). A next step 218 includes sending a pointer to the scheduled ad-hoc broadcast. A next step 220 includes broadcasting the network service provider information per the schedule.

摘要翻译： 一种用于在无线通信网络中传送系统信息的装置和方法。 第一步骤200包括定义单播阈值参数。 下一步骤201包括接收对系统信息的请求。 下一步骤202,204包括确定系统信息是否超过阈值参数。 如果系统信息超过阈值参数，则下一步骤206-216包括调度系统信息的自组播广播。 下一步骤218包括发送指向预定的自组播广播的指针。 下一步骤220包括根据时间表广播网络服务提供商信息。