公开(公告)号：US20180102289A1

公开(公告)日：2018-04-12

申请号：US15290569

申请日：2016-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  James W. Adkisson

IPC: H01L21/8222 ,  H01L27/082 ,  G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0274 ,  H01L21/8222 ,  H01L27/082 ,  H01L27/0823

Abstract: Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.

公开(公告)号：US20180069106A1

公开(公告)日：2018-03-08

申请号：US15806532

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/8228 ,  H01L27/082 ,  H01L21/8226 ,  H03F3/213 ,  H01L29/66 ,  H01L29/04 ,  H01L29/165 ,  H01L29/161 ,  H01L21/8222

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

公开(公告)号：US20170278955A1

公开(公告)日：2017-09-28

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L21/762 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US09590082B1

公开(公告)日：2017-03-07

申请号：US14965267

申请日：2015-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/08 ,  H01L29/737 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A first base layer is formed on a first device region of a substrate. A first emitter is formed that defines a first junction with the first base layer. A second base layer is formed on a second device region of a substrate. A second emitter is formed that defines a second junction with the second base layer. The first base layer and the second base layer differ in thickness, composition, concentration of an electrically-active dopant, or a combination thereof.

Abstract translation: 异质结双极晶体管的器件结构和制造方法。 第一基层形成在基板的第一器件区域上。 形成第一发射极，其限定与第一基极层的第一结。 第二基层形成在基板的第二器件区域上。 形成第二发射极，其限定与第二基极层的第二结。 第一基底层和第二基底层的厚度，组成，电活性掺杂剂的浓度或其组合不同。

公开(公告)号：US20160379930A1

公开(公告)日：2016-12-29

申请号：US14746891

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Ian A. McCallum-Cook

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5329

Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.

Abstract translation: 电熔丝和形成电熔丝的方法。 植入半导体衬底以限定半导体衬底中的改性区域。 围绕改性区域并且穿透到半导体衬底中的深度大于修饰区域的深度的沟槽形成在修改区域中，以便限定电熔丝的熔断体。 通过选择性蚀刻工艺从熔丝链下方去除衬底，其以比修改区域的第二蚀刻速率高的第一蚀刻速率去除半导体衬底。

公开(公告)号：US20160372548A1

公开(公告)日：2016-12-22

申请号：US14745764

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/73

CPC classification number: H01L29/0813 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 形成由第一半导体材料构成的基底层。 在基底层上形成由第二半导体材料构成的发射极层。 图案化发射极层以形成发射极指状物，其长度和宽度沿着发射极指的长度而变化。

公开(公告)号：US11749599B2

公开(公告)日：2023-09-05

申请号：US17097432

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/768 ,  H01L23/00 ,  H01L23/62

CPC classification number: H01L23/5258 ,  H01L21/76843 ,  H01L23/573 ,  H01L23/62 ,  H01L24/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

公开(公告)号：US10971597B2

公开(公告)日：2021-04-06

申请号：US16551061

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H01L29/737

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US10818772B2

公开(公告)日：2020-10-27

申请号：US15961364

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Pernell Dongmo ,  Cameron Luce ,  James W. Adkisson ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

公开(公告)号：US10777668B2

公开(公告)日：2020-09-15

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/06

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.