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    Replacement gate fabrication methods
    41.
    发明授权
    Replacement gate fabrication methods 有权
    替代门制造方法

    公开(公告)号：US08921904B2

    公开(公告)日：2014-12-30

    申请号：US14032567

    申请日：2013-09-20

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Peter Baars ,  Matthias Goldbach

    IPC: H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

    Abstract translation: 提供了半导体器件和相关的制造方法。 示例性的制造方法包括形成一对栅极结构，其具有布置在该对的第一栅极结构和该对的第二栅极结构之间的介质区域，并且在第一栅极结构和第二栅极结构之间的介电区域中形成空隙区域 门结构。 第一和第二栅极结构各自包括第一栅极电极材料，其中该方法通过去除第一栅电极材料继续，以提供对应于栅极结构的第二和第三空隙区域，并在第一空隙区域中形成第二栅电极材料， 第二空隙区域和第三空隙区域。

    SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE
    42.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE 有权
    包含自对准接触元件和更换栅极电极结构的半导体器件

    公开(公告)号：US20140203339A1

    公开(公告)日：2014-07-24

    申请号：US14226176

    申请日：2014-03-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

    Abstract translation: 半导体器件包括位于有源区上方的高k金属栅电极结构，具有位于栅极高度的顶表面，并且包括高k电介质材料和电极金属。 引出的漏极和源极区域横向邻近高k金属栅极电极结构定位并连接到有源区域，并且每个升高的漏极和源极区域的顶表面位于栅极下方的接触高度水平处 身高。 蚀刻停止层位于凸起的漏极和源极区域的顶表面上方，并且接触元件连接到凸起的漏极和源极区域之一，接触元件延伸穿过蚀刻停止层， k金属栅极电极结构和升高的漏极和源极区域。

    Semiconductor devices with replacement gate structures having conductive contacts positioned therebetween
    43.
    发明授权
    Semiconductor devices with replacement gate structures having conductive contacts positioned therebetween 有权
    具有替代栅极结构的半导体器件具有位于其间的导电接触

    公开(公告)号：US08742510B2

    公开(公告)日：2014-06-03

    申请号：US13718158

    申请日：2012-12-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

    IPC: H01L21/70 ,  H01L21/02 ,  H01L23/48 ,  H01L21/8238

    CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

    Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

    FDSOI semiconductor device with contact enhancement layer and method of manufacturing
    46.
    发明授权
    FDSOI semiconductor device with contact enhancement layer and method of manufacturing 有权

    公开(公告)号：US10347543B2

    公开(公告)日：2019-07-09

    申请号：US15810557

    申请日：2017-11-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

    Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

    FinFET based flash memory cell
    50.
    发明授权
    FinFET based flash memory cell 有权

    公开(公告)号：US10032891B2

    公开(公告)日：2018-07-24

    申请号：US15498652

    申请日：2017-04-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Baars ,  Juergen Faul

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L27/115 ,  H01L27/088 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/11536 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11521

    Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

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