公开(公告)号：US08039966B2

公开(公告)日：2011-10-18

申请号：US12553265

申请日：2009-09-03

申请人： Chih-Chao Yang ,  Chao-Kun Hu

发明人： Chih-Chao Yang ,  Chao-Kun Hu

IPC分类号： H01L29/40

CPC分类号： H01L21/76849 ,  C23C16/0272 ,  C23C16/16 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/54 ,  C23C28/00 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76883

摘要： A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms.

摘要翻译： 用于形成用于互连的原位金属/电介质盖的结构，工具和方法。 该方法包括形成嵌入在半导体衬底上的电介质层中的导线，该导线包括在铜芯的侧壁和底部上的铜芯和导电衬垫，该电线的顶表面与电介质的顶表面共面 层; 在铜芯的整个顶表面上形成金属盖; 在不将基底暴露于氧的情况下，在金属盖上形成电介质盖，衬垫的任何暴露部分和电介质层; 并且其中所述电介质盖是氧扩散阻挡层并且不含氧原子。

公开(公告)号：US07893520B2

公开(公告)日：2011-02-22

申请号：US12119125

申请日：2008-05-12

申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

IPC分类号： H01L29/00

CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

摘要翻译： 提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。 互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。 熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。 电介质覆盖层位于电介质材料和导电材料的顶部。 在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。 因此，当电流被提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

公开(公告)号：US20070087555A1

公开(公告)日：2007-04-19

申请号：US11163410

申请日：2005-10-18

申请人： Stephen Greco ,  Chao-Kun Hu ,  Paul McLaughlin

发明人： Stephen Greco ,  Chao-Kun Hu ,  Paul McLaughlin

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

公开(公告)号：US20060017169A1

公开(公告)日：2006-01-26

申请号：US11168559

申请日：2005-06-29

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  John Dukovic ,  Daniel Edelstein ,  Wilma Horkans ,  Chao-Kun Hu ,  Jeffrey Hurd ,  Kenneth Rodbell ,  Cyprian Uzoh ,  Kwong-Hon Wong

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  John Dukovic ,  Daniel Edelstein ,  Wilma Horkans ,  Chao-Kun Hu ,  Jeffrey Hurd ,  Kenneth Rodbell ,  Cyprian Uzoh ,  Kwong-Hon Wong

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： C25D3/38 ,  C25D5/022 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76885

摘要： A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

摘要翻译： 描述了用于集成电路芯片的亚微米互连结构的制造的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。 以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US06342733B1

公开(公告)日：2002-01-29

申请号：US09361573

申请日：1999-07-27

申请人： Chao-Kun Hu ,  Robert Rosenberg ,  Judith Marie Rubino ,  Carlos Juan Sambucetti ,  Anthony Kendall Stamper

发明人： Chao-Kun Hu ,  Robert Rosenberg ,  Judith Marie Rubino ,  Carlos Juan Sambucetti ,  Anthony Kendall Stamper

IPC分类号： H01L23522

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76864 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

公开(公告)号：US08232196B2

公开(公告)日：2012-07-31

申请号：US12608377

申请日：2009-10-29

申请人： Chih-Chao Yang ,  Chao-Kun Hu

发明人： Chih-Chao Yang ,  Chao-Kun Hu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49204

摘要： An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

摘要翻译： 一种互连结构，包括具有嵌入其中的第一导电材料的第一介电层的下部互连电平; 位于所述第一电介质层上的电介质覆盖层和所述第一导电材料的一些部分; 上部互连级别，包括具有填充有第二导电材料的至少一个通孔开口的第二介电层和填充有设置在其中的第二导电材料的至少一个覆盖的线路开口，其中所述至少一个通孔与第一导电材料接触 导电材料在下互连级别通过通孔气刨特征; 在所述至少一个通孔开口的侧壁上的电介质衬垫; 以及在所述至少一个通孔开口和所述至少一个覆盖线开口的侧壁和底部上的第一扩散阻挡层。 还提供了形成互连结构的方法。

公开(公告)号：US08133767B2

公开(公告)日：2012-03-13

申请号：US12976445

申请日：2010-12-22

申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

IPC分类号： H01L21/82

CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

摘要翻译： 提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。 互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。 熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。 电介质覆盖层位于电介质材料和导电材料的顶部。 在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。 因此，当电流被提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

公开(公告)号：US20100084767A1

公开(公告)日：2010-04-08

申请号：US12247632

申请日：2008-10-08

申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu ,  Surbhi Mittal

发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu ,  Surbhi Mittal

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/02362 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.

摘要翻译： 提供一种互连结构，其包括至少存在于嵌入在互连电介质材料中的至少一种导电材料的上表面的至少一部分上的含贵金属的盖。 在一个实施方案中，含贵金属的帽是不连续的，例如以至少一种导电材料的表面上的核或岛状存在。 在另一个实施方案中，含贵金属的盖在至少一种导电材料的表面上具有不均匀的厚度。

公开(公告)号：US07301236B2

公开(公告)日：2007-11-27

申请号：US11163410

申请日：2005-10-18

申请人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

发明人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

公开(公告)号：US06709562B1

公开(公告)日：2004-03-23

申请号：US09348632

申请日：1999-07-06

申请人： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  John Owen Dukovic ,  Daniel Charles Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth Parker Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

发明人： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  John Owen Dukovic ,  Daniel Charles Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth Parker Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

IPC分类号： C25D712

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/123 ,  H01L21/76877

摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

摘要翻译： 描述了用于制造用于集成电路芯片的亚微米互连结构的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。 以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。