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    Reusing sneak current in accessing memory cells
    41.
    发明授权
    Reusing sneak current in accessing memory cells 有权

    公开(公告)号：US10049733B2

    公开(公告)日：2018-08-14

    申请号：US15500062

    申请日：2014-10-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Naveen Muralimanohar ,  Erik Ordentlich ,  Yoocharn Jeon

    IPC: G11C13/00

    Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

    HIERARCHICAL COMPUTATIONS ON SPARSE MATRIX ROWS VIA A MEMRISTOR ARRAY
    42.
    发明申请
    HIERARCHICAL COMPUTATIONS ON SPARSE MATRIX ROWS VIA A MEMRISTOR ARRAY 审中-公开

    公开(公告)号：US20180173677A1

    公开(公告)日：2018-06-21

    申请号：US15380269

    申请日：2016-12-15

    Applicant: Hewlett Packard Enterprise development LP

    Inventor： Naveen Muralimanohar

    IPC: G06F17/16 ,  G06F7/523

    CPC classification number: G06F7/523 ,  G06F7/5443 ,  G06J1/00

    Abstract: Hierarchical computation on sparse matrix rows is disclosed. One example is a circuit including a sparse row processor to identify a sparse row of a matrix, where the identified row has a number of non-zero entries less than a threshold, associate a sub-vector of an input vector with a sub-row of the identified row, where the sub-row comprises the non-zero entries of the identified row, and where entries in the sub-vector correspond to the non-zero entries in the identified row in a multiplication operation, and map entries in the matrix to an engine formed from a memristor array. A stream buffer queues sub-vectors based on a position of associated sub-rows of identified sparse rows. The engine computes analog multiplication results between sub-rows and their associated sub-vectors, where each column of the array is configured to hierarchically compute multiple multiplication results based on the queue.

    DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY
    45.
    发明申请
    DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY 审中-公开

    公开(公告)号：US20170271001A1

    公开(公告)日：2017-09-21

    申请号：US15500040

    申请日：2015-01-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Naveen Muralimanohar ,  Rajeev Balasubramonian ,  Martin Foltin

    IPC: G11C13/00

    Abstract: A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.

    CACHE MANAGEMENT FOR NONVOLATILE MAIN MEMORY
    47.
    发明申请
    CACHE MANAGEMENT FOR NONVOLATILE MAIN MEMORY 审中-公开

    公开(公告)号：US20170192886A1

    公开(公告)日：2017-07-06

    申请号：US15325255

    申请日：2014-07-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Hans Boehm ,  Naveen Muralimanohar

    IPC: G06F12/0804 ,  G06F12/0815

    Abstract: A coherence logic of a first core in a multi-core processor receives a request to send a cache line to a second core in the multi-core processor. In response to receiving the request, the coherence logic determines if the cache line is associated to a logically nonvolatile virtual page mapped to a nonvolatile physical page in a nonvolatile main memory. If so, the coherence logic flushes the cache line from the cache to the nonvolatile main memory and then sends the cache line to the second core.

    Memristive dot product circuit based floating point computations
    49.
    发明授权
    Memristive dot product circuit based floating point computations 有权

    公开(公告)号：US11157237B2

    公开(公告)日：2021-10-26

    申请号：US16189291

    申请日：2018-11-13

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Naveen Muralimanohar ,  Benjamin Feinberg

    IPC: G06F7/487 ,  G06F5/01 ,  G11C13/00 ,  H03M7/24 ,  G06F17/16

    Abstract: In some examples, memristive dot product circuit based floating point computations may include ascertaining a matrix and a vector including floating point values, and partitioning the matrix into a plurality of sub-matrices according to a size of a plurality of memristive dot product circuits. For each sub-matrix of the plurality of sub-matrices, the floating point values may be converted to fixed point values. Based on the conversion and selected ones of the plurality of memristive dot product circuits, a dot product operation may be performed with respect to a sub-matrix and the vector. Each ones of the plurality of memristive dot product circuits may include rows including word line voltages corresponding to the floating point values of the vector, conductances corresponding to the floating point values of an associated sub-matrix, and columns that include bitline currents corresponding to dot products of the voltages and conductances.

    Floating point data set compression
    50.
    发明授权
    Floating point data set compression 有权

    公开(公告)号：US11018692B2

    公开(公告)日：2021-05-25

    申请号：US16942293

    申请日：2020-07-29

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Anirban Nag ,  Naveen Muralimanohar ,  Paolo Faraboschi

    IPC: H03M7/30 ,  H03M7/24

    Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

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