公开(公告)号：US20060170028A1

公开(公告)日：2006-08-03

申请号：US11323355

申请日：2005-12-30

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US20080130367A1

公开(公告)日：2008-06-05

申请号：US12027735

申请日：2008-02-07

申请人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

发明人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

IPC分类号： G11C16/14

CPC分类号： G11C7/18 ,  G11C16/16 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

摘要翻译： 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

公开(公告)号：US20080089136A1

公开(公告)日：2008-04-17

申请号：US11870762

申请日：2007-10-11

申请人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

发明人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

摘要翻译： 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。

公开(公告)号：US20080008003A1

公开(公告)日：2008-01-10

申请号：US11789003

申请日：2007-04-23

申请人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

发明人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

摘要翻译： 非易失性存储器件包括存储器单元块，第一切换块和第二切换块。 多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管 它连接到源线。 第一切换块选择性地将全局位线连接到本地位线，并且第二切换块以预定位数为单位来控制存储单元块中的存储单元。 第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

公开(公告)号：US20080003810A1

公开(公告)日：2008-01-03

申请号：US11823381

申请日：2007-06-27

申请人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

发明人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC分类号： H01L21/4763

CPC分类号： H01L27/1021

摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

摘要翻译： 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US20070091682A1

公开(公告)日：2007-04-26

申请号：US11427211

申请日：2006-06-28

申请人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

发明人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

摘要翻译： 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

公开(公告)号：US20060244042A1

公开(公告)日：2006-11-02

申请号：US11413640

申请日：2006-04-28

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.

摘要翻译： 在分闸式非易失存储器件及其制造方法中， 辅助层图案设置在半导体衬底的源极区域上。 由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。 因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

公开(公告)号：US20150155024A1

公开(公告)日：2015-06-04

申请号：US14448717

申请日：2014-07-31

申请人： Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

发明人： Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1659

摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

摘要翻译： 磁存储器件包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。 磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。 还描述了相关系统和操作方法。

公开(公告)号：US08110873B2

公开(公告)日：2012-02-07

申请号：US12339448

申请日：2008-12-19

申请人： Sung-Gon Choi ,  Hee-Seog Jeon

发明人： Sung-Gon Choi ,  Hee-Seog Jeon

IPC分类号： H01L21/76

CPC分类号： H01L29/0847 ,  H01L21/76895 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7835

摘要： A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.

摘要翻译： 一种高电压晶体管，包括限定有源区的衬底，所述有源区中的第一杂质区和第二杂质区以及所述第一和第二杂质区之间的第三杂质区，以及所述有源区上的第一栅电极 在第一杂质区域和第三杂质区域之间的有源区域上的第二栅电极和第二杂质区域之间的有源区域上的第二栅电极。

公开(公告)号：US20100265765A1

公开(公告)日：2010-10-21

申请号：US12662431

申请日：2010-04-16

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

IPC分类号： G11C16/02 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0433 ,  G11C16/24

摘要： A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

摘要翻译： 提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。 连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平 在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。 因此，可以抑制由FN隧穿和结热电子引起的程序干扰。