公开(公告)号：US07915686B2

公开(公告)日：2011-03-29

申请号：US11439260

申请日：2006-05-24

申请人： Yasuhiro Shimamoto ,  Jiro Yugami ,  Masao Inoue ,  Masaharu Mizutani

发明人： Yasuhiro Shimamoto ,  Jiro Yugami ,  Masao Inoue ,  Masaharu Mizutani

IPC分类号： H01L29/76

CPC分类号： H01L27/092 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.

摘要翻译： 本发明的目的是提高具有CMISFET的半导体器件的性能。 形成CMISFET的n沟道MISFET和p沟道MISFET中的每一个包括由氮氧化硅膜和包括位于栅极绝缘膜上的硅膜的栅电极构成的栅极绝缘膜。 诸如Hf之类的金属元素以1×1013至5×1014原子/ cm2的表面密度引入栅电极和栅绝缘膜之间的界面附近。 n沟道MISFET和p沟道MISFET的沟道区域的杂质浓度被控制在等于或低于1.2×1018 / cm3。

公开(公告)号：US20110057265A1

公开(公告)日：2011-03-10

申请号：US12943600

申请日：2010-11-10

申请人： Shinsuke SAKASHITA ,  Takaaki Kawahara ,  Jiro Yugami

发明人： Shinsuke SAKASHITA ,  Takaaki Kawahara ,  Jiro Yugami

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.

摘要翻译： 提供一种高度可靠的半导体器件，其分别配备有具有期望特性的多个半导体元件; 以及便于制造半导体器件的制造方法。 半导体器件通过在栅极绝缘膜的整个上表面上形成厚度为3至30nm的栅电极金属膜来制造; 通过使用与栅电极金属膜不同的材料，在属于nFET区域的栅极金属膜的一部分的整个上表面上形成厚度为10nm以下的n侧覆盖层; 在n侧盖层上进行热处理，将n侧盖层的材料向n侧盖层正下方的栅电极金属膜扩散，形成n侧栅电极 金属膜在nFET区域。 然后沉积多晶硅层，随后进行栅电极处理。

公开(公告)号：US07855134B2

公开(公告)日：2010-12-21

申请号：US12354434

申请日：2009-01-15

申请人： Shinsuke Sakashita ,  Takaaki Kawahara ,  Jiro Yugami

发明人： Shinsuke Sakashita ,  Takaaki Kawahara ,  Jiro Yugami

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842

摘要： Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.

摘要翻译： 提供一种高度可靠的半导体器件，其分别配备有具有期望特性的多个半导体元件; 以及便于制造半导体器件的制造方法。 半导体器件通过在栅极绝缘膜的整个上表面上形成厚度为3至30nm的栅电极金属膜来制造; 通过使用与栅电极金属膜不同的材料，在属于nFET区域的栅极金属膜的一部分的整个上表面上形成厚度为10nm以下的n侧覆盖层; 在n侧盖层上进行热处理，将n侧盖层的材料向n侧盖层正下方的栅电极金属膜扩散，形成n侧栅电极 金属膜在nFET区域。 然后沉积多晶硅层，随后进行栅电极处理。

公开(公告)号：US20090218634A1

公开(公告)日：2009-09-03

申请号：US12354434

申请日：2009-01-15

申请人： Shinsuke Sakashita ,  Takaaki Kawahara ,  Jiro Yugami

发明人： Shinsuke Sakashita ,  Takaaki Kawahara ,  Jiro Yugami

IPC分类号： H01L27/092 ,  H01L21/3205

CPC分类号： H01L21/823842

摘要： Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.

摘要翻译： 提供一种高度可靠的半导体器件，其分别配备有具有期望特性的多个半导体元件; 以及便于制造半导体器件的制造方法。 半导体器件通过在栅极绝缘膜的整个上表面上形成厚度为3至30nm的栅电极金属膜来制造; 通过使用与栅电极金属膜不同的材料，在属于nFET区域的栅极金属膜的一部分的整个上表面上形成厚度为10nm以下的n侧覆盖层; 在n侧盖层上进行热处理，将n侧盖层的材料向n侧盖层正下方的栅电极金属膜扩散，形成n侧栅电极 金属膜在nFET区域。 然后沉积多晶硅层，随后进行栅电极处理。

公开(公告)号：US07193281B2

公开(公告)日：2007-03-20

申请号：US11296289

申请日：2005-12-08

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L29/76

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。

公开(公告)号：US20060208325A1

公开(公告)日：2006-09-21

申请号：US11373112

申请日：2006-03-13

申请人： Masaharu Mizutani ,  Masao Inoue ,  Jiro Yugami ,  Junichi Tsuchimoto ,  Koji Nomura ,  Yasuhiro Shimamoto

发明人： Masaharu Mizutani ,  Masao Inoue ,  Jiro Yugami ,  Junichi Tsuchimoto ,  Koji Nomura ,  Yasuhiro Shimamoto

IPC分类号： H01L29/94

CPC分类号： H01L29/7833 ,  H01L29/1083 ,  H01L29/6659

摘要： A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.

摘要翻译： MISFET包括：具有杂质浓度C的沟道区的p型衬底; 形成在沟道区上的由SiO 2构成的绝缘膜; 以及由栅极绝缘膜形成的由HfSiON构成的绝缘膜。 当存在假设的MISFET，其包括具有杂质浓度C并且由与衬底相同的材料制成的沟道区域和由沟道区域上形成的仅由SiON制成的绝缘膜的假定衬底时，沟道区的杂质浓度C 使得所述沟道区中的电子的迁移率的最大值高于假定沟道区中的电子的迁移率的最大值。 因此，可以降低电源电压并且可以降低功耗。

公开(公告)号：US06833582B2

公开(公告)日：2004-12-21

申请号：US10766188

申请日：2004-01-29

申请人： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

发明人： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

公开(公告)号：US06833296B2

公开(公告)日：2004-12-21

申请号：US10776215

申请日：2004-02-12

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。

公开(公告)号：US06777296B2

公开(公告)日：2004-08-17

申请号：US10321501

申请日：2002-12-18

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Hirotaka Hamamura

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Hirotaka Hamamura

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： Disclosed is a method of improving smoothness on a surface of a gate dielectric composed of a high dielectric film made of metal oxide. A dielectric film with a high permittivity made of metal oxide such as a TiO2 film or a ZrO2 film having an amorphous structure is deposited over a silicon substrate by the plasma enhanced chemical vapor deposition method, and the film is used as a gate dielectric. Since the gate dielectric has good surface smoothness, simultaneous reductions of both the film thickness of a gate dielectric and the gate leakage current can be achieved. In addition, it is also possible to reduce the variation in the characteristics of the devices.

摘要翻译： 公开了一种提高由金属氧化物构成的高电介质膜构成的栅极电介质的表面的平滑度的方法。 通过等离子体增强化学气相沉积法在硅衬底上沉积具有由诸如TiO 2膜或具有无定形结构的ZrO 2膜的金属氧化物的高介电常数的介电膜，并且该膜用作栅极电介质。 由于栅极电介质具有良好的表面平滑度，因此可以实现栅极电介质的膜厚度和栅极漏电流的同时减小。 此外，还可以减小装置的特性的变化。