公开(公告)号：US08680605B2

公开(公告)日：2014-03-25

申请号：US13112443

申请日：2011-05-20

申请人： Sang-hun Jeon ,  Ho-jung Kim

发明人： Sang-hun Jeon ,  Ho-jung Kim

IPC分类号： H01L29/792 ,  H01L21/336 ,  G11C16/04

CPC分类号： H01L27/11551 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.

摘要翻译： 堆叠式存储器件可以包括至少一个存储器单元和布置在至少一个存储器单元的上方或下方的至少一个外围电路单元。 所述至少一个存储器单元可以包括存储器串阵列，多个位线以及多个串选择焊盘。 存储器串可以包括排列成矩阵的多个存储器串，并且每个存储器串可以包括多个存储单元和垂直于衬底布置的串选择装置。 多个位线可以在第一方向上延伸并且可以连接到多个存储器串的端部。 多个串选择板可以沿着第一方向排列成单行，并且可以连接到包括在多个存储器串中的串选择装置。

公开(公告)号：US08406029B2

公开(公告)日：2013-03-26

申请号：US12658859

申请日：2010-02-16

申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

IPC分类号： G11C19/00

CPC分类号： G11C19/0808 ,  G11C11/14 ,  G11C19/0841

摘要： In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.

摘要翻译： 在存储器装置和用于控制存储器件的方法中，存储器件包括将结构存储在磁性结构的多个域中的磁性结构。 读取单元通过向磁性结构施加读取电流来从磁性结构的多个域中的至少一个域读取信息。 位置检测器单元将来自读取单元的读取电流读取的信息与磁性结构的多个域的多个域进行比较，以识别多个域的选定域处的预期信息模式的存在。

公开(公告)号：US20100246234A1

公开(公告)日：2010-09-30

申请号：US12654645

申请日：2009-12-28

申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C13/0023 ,  G11C2213/71 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.

摘要翻译： 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个解码器电连接到多个存储器层并且布置在多个存储器层中的相应的一个 所述多个组以及至少一个预解码器电连接到所述多个解码器并且设置在所述多个解码器之间。 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个驱动器电连接到多个存储器层并且被布置在多个存储器层中的相应的一个 所述多个组，以及电连接到所述多个驱动器之间的至少一个预驱动器，并且设置在所述多个驱动器之间。

公开(公告)号：US20100208504A1

公开(公告)日：2010-08-19

申请号：US12658859

申请日：2010-02-16

申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

IPC分类号： G11C19/00 ,  G11C7/00

CPC分类号： G11C19/0808 ,  G11C11/14 ,  G11C19/0841

摘要： In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.

摘要翻译： 在存储器装置和用于控制存储器件的方法中，存储器件包括将结构存储在磁性结构的多个域中的磁性结构。 读取单元通过向磁性结构施加读取电流来从磁性结构的多个域中的至少一个域读取信息。 位置检测器单元将来自读取单元的读取电流读取的信息与磁性结构的多个域的多个域进行比较，以识别多个域的选定域处的预期信息模式的存在。

公开(公告)号：US20080123432A1

公开(公告)日：2008-05-29

申请号：US11606932

申请日：2006-12-01

申请人： Ho-jung Kim

发明人： Ho-jung Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/26

摘要： A method of reading data from a flash memory device that includes a multiple block memory cell array, each block having a cell string connected to a bit line and comprising a string select transistor connected to a string select line, a memory cell connected to a wordline and a global select transistor connected to a global select line and having a source connected to a common source line. The method includes pre-charging the bit lines to a first voltage in a standby state, discharging a selected bit line connected to a selected memory cell to a second voltage in response to a read command, and reading data stored in the selected memory cell in response to the read command.

摘要翻译： 一种从包括多块存储单元阵列的闪速存储器件读取数据的方法，每个块具有连接到位线的单元串，并且包括连接到串选择线的串选择晶体管，连接到字线的存储单元 以及连接到全局选择线并具有连接到公共源极线的源极的全局选择晶体管。 该方法包括将待机状态下的位线预充电到第一电压，响应于读取命令将连接到所选择的存储器单元的选定位线放电到第二电压，以及读取存储在所选存储单元中的数据 对读命令的响应。

公开(公告)号：US20070008806A1

公开(公告)日：2007-01-11

申请号：US11481363

申请日：2006-07-05

申请人： Ho-jung Kim

发明人： Ho-jung Kim

IPC分类号： G11C8/00

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C8/10

摘要： Provided is a word line decoder suitable to a low operating voltage of a flash memory device. The word line decoder generates a block word line driving signal of a high voltage in response to a block selection signal. The word line decoder includes a first inverter receiving the block selection signal, a second inverter receiving an output of the first inverter, and first and second serially connected transistors receiving an output of the second inverter and outputting the block word line driving signal. The gates of the first and second transistors are connected to a supply voltage terminal. The word line decoder includes a third transistor having a source connected to a high voltage terminal and a gate connected to a line transmitting the block word line driving signal, a fourth transistor connected between the drain of the third transistor and the block word line driving signal line, a fifth transistor connected between the drain of the third transistor and the gate of the fourth transistor and having a gate connected to the block word line driving signal line, and a sixth transistor connected between the output of the first inverter and the gate of the second transistor and having a gate connected to the supply voltage terminal.

摘要翻译： 提供了适用于闪存器件的低工作电压的字线解码器。 字线解码器响应于块选择信号产生高电压的块字线驱动信号。 字线解码器包括接收块选择信号的第一反相器，接收第一反相器的输出的第二反相器和接收第二反相器的输出的第一和第二串联连接的晶体管，并输出块字线驱动信号。 第一和第二晶体管的栅极连接到电源电压端子。 字线解码器包括具有连接到高电压端子的源极和连接到发送块字线驱动信号的线路的栅极的第三晶体管，连接在第三晶体管的漏极和块字线驱动信号之间的第四晶体管 连接在第三晶体管的漏极和第四晶体管的栅极之间并且具有连接到块字线驱动信号线的栅极的第五晶体管，以及连接在第一反相器的输出和第一反相器的栅极之间的第六晶体管 第二晶体管并且具有连接到电源电压端子的栅极。

公开(公告)号：US20110286275A1

公开(公告)日：2011-11-24

申请号：US13112443

申请日：2011-05-20

申请人： Sang-hun Jeon ,  Ho-jung Kim

发明人： Sang-hun Jeon ,  Ho-jung Kim

IPC分类号： G11C16/04 ,  H01L21/28

CPC分类号： H01L27/11551 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.

摘要翻译： 堆叠式存储器件可以包括至少一个存储器单元和布置在至少一个存储器单元的上方或下方的至少一个外围电路单元。 所述至少一个存储器单元可以包括存储器串阵列，多个位线以及多个串选择焊盘。 存储器串可以包括排列成矩阵的多个存储器串，并且每个存储器串可以包括多个存储单元和垂直于衬底布置的串选择装置。 多个位线可以在第一方向上延伸并且可以连接到多个存储器串的端部。 多个串选择板可以沿着第一方向排列成单行，并且可以连接到包括在多个存储器串中的串选择装置。

公开(公告)号：US20110273221A1

公开(公告)日：2011-11-10

申请号：US13064264

申请日：2011-03-15

申请人： Ho-jung Kim ,  Jae-kwang Shin ,  Jae-Joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang ,  Ki-ha Hong

发明人： Ho-jung Kim ,  Jae-kwang Shin ,  Jae-Joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang ,  Ki-ha Hong

IPC分类号： H03K17/284 ,  H03K17/687

CPC分类号： H03K17/163 ,  H03K17/284

摘要： A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

摘要翻译： 功率器件包括具有控制端子和输出端子的开关器件; 以及驱动电路，被配置为向控制端子提供驱动电压，使得控制端子和输出端子之间的电压保持小于或等于临界电压。 根据开关装置的电流 - 电压特性来确定驱动电压达到目标电平所需的上升时间。 而且，当控制端子与输出端子之间的电压超过临界电压时，控制端子与输出端子之间产生漏电流。

公开(公告)号：US20080112227A1

公开(公告)日：2008-05-15

申请号：US11606246

申请日：2006-11-30

申请人： Ho-jung Kim

发明人： Ho-jung Kim

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/28

摘要： A non-volatile memory device includes a memory cell array and a voltage control unit. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings. Each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor serially connected between the first selection transistor and the second selection transistor. The voltage control unit provides first selection line voltages and word line voltages to first selection lines connected to the first selection transistors and word lines connected to the memory cell transistors, respectively, in response to a plurality of block selection signals corresponding to the plurality of memory blocks, and provides a second selection line voltage directly to second selection lines connected to the second selection transistors independently of the block selection signals

摘要翻译： 非易失性存储器件包括存储单元阵列和电压控制单元。 存储单元阵列包括多个存储块，每个存储块包括多个单元串。 每个单元串包括第一选择晶体管，第二选择晶体管和串联连接在第一选择晶体管和第二选择晶体管之间的至少一个存储单元晶体管。 电压控制单元响应于对应于多个存储器的多个块选择信号，分别向连接到第一选择晶体管的第一选择线和连接到存储单元晶体管的字线提供第一选择线电压和字线电压 并且独立于块选择信号，直接向连接到第二选择晶体管的第二选择线提供第二选择线电压

公开(公告)号：US20080101128A1

公开(公告)日：2008-05-01

申请号：US11605225

申请日：2006-11-29

申请人： Ho-jung Kim

发明人： Ho-jung Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/24

摘要： A nonvolatile memory device includes a memory cell array and a voltage controller. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings, where each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor connected in series between the first and second selection transistors. The voltage controller applies a first selection voltage to first selection lines connected to the first selection transistors, a second selection voltage to second selection lines connected to the second selection transistors, and a word line voltage to word lines connected to the memory cell transistors, in response to a plurality of block selection signals corresponding to the memory blocks. The voltage controller precharges the second selection lines to a precharge voltage by applying the second selection line voltage to the second selection lines in a standby state, where the second selection line voltage is equal to the precharge voltage.

摘要翻译： 非易失性存储器件包括存储单元阵列和电压控制器。 存储单元阵列包括多个存储块，每个存储块包括多个单元串，其中每个单元串包括第一选择晶体管，第二选择晶体管和串联连接在第一和第二单元串之间的至少一个存储单元晶体管 选择晶体管。 电压控制器对连接到第一选择晶体管的第一选择线，连接到第二选择晶体管的第二选择线的第二选择电压和连接到存储单元晶体管的字线的字线电压施加第一选择电压， 响应于对应于存储块的多个块选择信号。 电压控制器通过在第二选择线电压等于预充电电压的待机状态下将第二选择线电压施加到第二选择线，将第二选择线预充电到预充电电压。