公开(公告)号：US20080128793A1

公开(公告)日：2008-06-05

申请号：US12017064

申请日：2008-01-21

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

摘要翻译： 一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。 电荷捕获层和控制栅极设置在衬底上。 电介质层设置在基板，电荷俘获层和控制栅极之间。 源极和漏极设置在电荷俘获层的每一侧上的衬底中。 轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。 掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。 由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

公开(公告)号：US20080099826A1

公开(公告)日：2008-05-01

申请号：US11588830

申请日：2006-10-27

申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chih Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chih Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.

摘要翻译： 存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

公开(公告)号：US20080025087A1

公开(公告)日：2008-01-31

申请号：US11460497

申请日：2006-07-27

申请人： Yen-Hao Shih ,  Jung-Yu Hsieh ,  Yi-Lin Yang ,  Chia-Hua Chang ,  Jenn-Gwo Hwu

发明人： Yen-Hao Shih ,  Jung-Yu Hsieh ,  Yi-Lin Yang ,  Chia-Hua Chang ,  Jenn-Gwo Hwu

IPC分类号： G11C16/04

CPC分类号： H01L21/76838 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the device fabrication process. The annealing process is conducted at a temperature of about 350° C. to 450° C. and with the concentration of the hydrogen gas greater than 0.5 mole percent.

摘要翻译： 提供了一种电荷俘获存储器件的制造方法。 该方法包括形成至少具有电荷捕获介质的堆叠结构。 然后在器件制造过程之后对堆叠结构进行氢气中的退火处理。 退火过程在约350℃至450℃的温度下进行，氢气的浓度大于0.5摩尔％。

公开(公告)号：US20060284243A1

公开(公告)日：2006-12-21

申请号：US11146777

申请日：2005-06-06

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/7885 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/90

摘要： An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.

摘要翻译： 不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。 复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。 非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。 非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。 还描述了制造非对称掺杂的存储单元的方法。

公开(公告)号：US20060226467A1

公开(公告)日：2006-10-12

申请号：US11100518

申请日：2005-04-07

申请人： Hang-Ting Lue ,  Min-Ta Wu ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

发明人： Hang-Ting Lue ,  Min-Ta Wu ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/4232 ,  H01L29/792

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first inversion region, a second inversion region, and a channel region between the first inversion region and the second inversion region. The semiconductor device further includes a control gate over the channel region and at least one sub-gate over the first and second inversion regions, wherein the control gate does not extend over the at least one sub-gate.

摘要翻译： 半导体器件包括半导体衬底。 半导体衬底包括第一反转区域，第二反转区域和第一反转区域和第二反转区域之间的沟道区域。 所述半导体器件还包括在所述沟道区上的控制栅极以及所述第一和第二反转区域上的至少一个子栅极，其中所述控制栅极不在所述至少一个子栅极上延伸。

公开(公告)号：US20060133153A1

公开(公告)日：2006-06-22

申请号：US11016666

申请日：2004-12-17

申请人： Yen-Hao Shih ,  Hang-Ting Lue

发明人： Yen-Hao Shih ,  Hang-Ting Lue

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0466 ,  G11C16/3418

摘要： A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a transistor control gate and a transistor channel region. The method further comprises applying a negative voltage bias to the transistor control gate. In another embodiment, the method further comprises performing a baking process on the memory device. The method further comprises performing a memory operation on the memory device.

摘要翻译： 稳定存储器件的方法包括在存储器件的电荷俘获层中俘获多个电荷。 电荷捕获层位于晶体管控制栅极和晶体管沟道区域之间。 该方法还包括向晶体管控制栅极施加负电压偏置。 在另一个实施例中，该方法还包括在存储器件上执行烘焙处理。 该方法还包括对存储器设备执行存储器操作。

公开(公告)号：US20050237815A1

公开(公告)日：2005-10-27

申请号：US10876377

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/14 ,  G11C16/30 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/30

摘要： A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tending to the induce balanced charge tunneling between the gate and the charge trapping structure and between the charge trapping structure in the channel. A second procedure (typically program) is used to establish a high threshold state in the memory cell, including a third bias arrangement that causes an increase in negative charge in the charge trapping structure.

摘要翻译： 一种操作存储器单元的方法包括施加第一过程（通常是擦除）以建立低阈值状态，包括引起电荷俘获结构中的负电荷减小的第一偏置装置，以及倾向于引起平衡电荷隧穿的第二偏置装置 在栅极和电荷捕获结构之间以及沟道中的电荷捕获结构之间。 第二程序（通常为程序）用于在存储器单元中建立高阈值状态，包括导致电荷俘获结构中的负电荷增加的第三偏置装置。

公开(公告)号：US08987098B2

公开(公告)日：2015-03-24

申请号：US13527259

申请日：2012-06-19

申请人： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

发明人： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC分类号： H01L21/336 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11565

摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

摘要翻译： 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US08759899B1

公开(公告)日：2014-06-24

申请号：US13739914

申请日：2013-01-11

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC分类号： H01L29/788

CPC分类号： H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

摘要翻译： 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20130175598A1

公开(公告)日：2013-07-11

申请号：US13347331

申请日：2012-01-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

摘要翻译： 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。