公开(公告)号：US07075848B2

公开(公告)日：2006-07-11

申请号：US10889194

申请日：2004-07-12

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C17/18

CPC分类号： G11C29/812 ,  G11C29/806

摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

摘要翻译： 一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址 在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

公开(公告)号：US20050195633A1

公开(公告)日：2005-09-08

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/10 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

公开(公告)号：US06781899B2

公开(公告)日：2004-08-24

申请号：US10202272

申请日：2002-07-24

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Hyou-Youn Nam

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Hyou-Youn Nam

IPC分类号： G11C2900

CPC分类号： G11C29/12005 ,  G11C11/41 ,  G11C29/12 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.

摘要翻译： 半导体存储器件采用电源系统，其中提供给单元区域的第一电源电压与提供给外围电路区域的第二电源电压分离。 特别地，在晶片老化测试操作模式期间，提供给单元区域的第一电源电压高于提供给外围电路区域的第二电源电压。 如果在第二电源系统下执行晶片老化测试操作，则可以切断由存储器单元的闩锁现象形成的直流电流路径。

公开(公告)号：US5956279A

公开(公告)日：1999-09-21

申请号：US19519

申请日：1998-02-05

申请人： Hyun-Sun Mo ,  Choong-Keun Kwak

发明人： Hyun-Sun Mo ,  Choong-Keun Kwak

IPC分类号： G11C11/413 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A static random access memory (SRAM) device comprises an array of memory cells, a plurality of bit line precharge circuit for selectively delivering current to bit lines in response to a pair of control signals, during normal and burn-in test modes, and a burn-in current source circuit for selectively delivering current to the memory cells selected by the word lines along with the precharge circuit, in response to the control signals, during the burn-in test mode. In burn-in write operation, memory cells can be supplied with enough cell current without large increasing of chip size and power consumption in normal operation mode.

摘要翻译： 静态随机存取存储器（SRAM）装置包括存储器单元阵列，多个位线预充电电路，用于在正常和老化测试模式期间响应于一对控制信号选择性地将电流输送到位线;以及 老化电流源电路，用于在老化测试模式期间响应于控制信号选择性地将电流与预充电电路一起输送到由字线选择的存储器单元。 在老化写入操作中，在正常操作模式下，存储单元可以提供足够的单元电流，而不会大大增加芯片尺寸和功耗。

公开(公告)号：US5471429A

公开(公告)日：1995-11-28

申请号：US348180

申请日：1994-11-28

申请人： Seung-Keun Lee ,  Choong-Keun Kwak

发明人： Seung-Keun Lee ,  Choong-Keun Kwak

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  H01L21/66 ,  G11C7/00

CPC分类号： G11C29/34 ,  G01R31/2856

摘要： The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM. The semiconductor memory device according to the present invention, which includes a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, and a column decoder for selecting the column of the memory cell array, comprises an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, and a burn-in control circuit for inputting the output signal of the read/write control circuit, supplying a burn-in signal responsive to the data input through the input/output line control circuit to the row decoder and column decoder, and enabling a burn-in test of the same chip after a package process.

摘要翻译： 本发明涉及半导体存储器件，更具体地说，涉及提高静态随机存取存储器RAM的可靠性的这种器件的老化电路和老化方法。 根据本发明的半导体存储器件，其包括存储单元阵列，其中多个存储器单元被存储在行和列的方向上，行解码器用于选择存储单元阵列的行，以及列解码器 用于选择存储单元阵列的列，包括形成在设置在同一芯片上的数据输入/输出引脚和存储单元阵列的列之间的输入/输出线控制电路，用于发送通过数据输入/ 输出引脚，用于将控制存储单元阵列中的数据的输入/输出的信号提供给输入/输出线控制电路的读/写控制电路，以及用于输入读/写控制电路的输出信号的老化控制电路， 写入控制电路，响应于通过输入/输出线路控制电路输入的数据向行解码器和列解码器提供老化信号，以及在一个包之后启用相同芯片的老化测试 年龄过程。

公开(公告)号：US07110286B2

公开(公告)日：2006-09-19

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US20060104102A1

公开(公告)日：2006-05-18

申请号：US11183613

申请日：2005-07-18

申请人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/18

摘要： A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

摘要翻译： 真正的位线可以沿第一方向跨越存储器件的存储器单元区域延伸，并且互补位线可以在与第一方向相反的第二方向跨越存储器单元区域延伸，其中真位线和互补位线 包括位线对。

公开(公告)号：US06928022B2

公开(公告)日：2005-08-09

申请号：US10969697

申请日：2004-10-20

申请人： Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/12 ,  G11C16/30 ,  G11C29/02 ,  H01L27/105 ,  H01L45/00 ,  G11C17/18

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C29/02 ,  G11C29/028 ,  G11C2013/0078 ,  G11C2029/5006 ,  G11C2213/79

摘要： A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell having a phase change property shift due to an external factor or due a process change. The write driver circuit includes a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit. Each of the first and second programmable current paths includes fuses that can be programmed to adjust their resistance to adjust the respective selected output voltage to compensate for the current output shift in the write current generation circuit or for the phase change memory cell having the phase change property shift.

摘要翻译： 一种写入驱动器电路，包括用于相变存储器件的多个可编程保险丝，其中即使在写入电流产生电路中的电流输出移位的情况下也正确地执行写入操作; 或者由于外部因素或由于处理变化而具有相变特性偏移的相变存储单元的情况。 写入驱动器电路包括：写入电流控制单元，用于通过选择第一或第二可选择电流路径中的一个，基于是否应用第一或第二选择脉冲信号来输出所选择的第一或第二电平电平; 以及电流驱动单元，用于产生由写入电流控制单元的输出电压控制的写入电流。 第一和第二可编程电流路径中的每一个包括熔丝，其可以被编程以调整其电阻以调整相应的选择的输出电压以补偿写入电流产生电路中的电流输出偏移或具有相变的相变存储器单元 财产转移

公开(公告)号：US20050007843A1

公开(公告)日：2005-01-13

申请号：US10889194

申请日：2004-07-12

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/812 ,  G11C29/806

摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

摘要翻译： 一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址 在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

公开(公告)号：US06456547B1

公开(公告)日：2002-09-24

申请号：US09689098

申请日：2000-10-12

申请人： Hyun-Sun Mo ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Hyun-Sun Mo ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C700

CPC分类号： G11C29/83 ,  G11C7/12

摘要： A semiconductor memory device having memory cells connected with pairs of bit lines and word lines comprises a pre-charging part for pre-charging a pair of bit lines in response to a first state control signal at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating a second state control signal to the pre-charging part when a stand-by current failure occurs due to defect in the pair of bit lines, wherein the second state control signal is independent of a pre-charge relating signal externally applied and the pre-charging part cuts-off a supply voltage from being applied to the pair of bit lines with defect; and a bit line floating prevent part for compensatively fixing potential values of the pair of bit lines with defect so that a cell supply voltage is prevented from being applied to the pair of bit lines with defect at a memory access mode of the semiconductor memory device, so that a hard type defect like a stand-by current failure can be repaired regardless of a logic state of a pre-charge control signal, thereby reducing the probability of occurrence of defect in a semiconductor memory device.

摘要翻译： 具有与位线对和字线对连接的存储单元的半导体存储器件包括预充电部分，用于响应于半导体存储器件的待机模式下的第一状态控制信号对一对位线进行预充电 ; 位线充电控制部分，用于当由于一对位线中的缺陷而发生待机电流故障时，向预充电部分产生第二状态控制信号，其中第二状态控制信号独立于预充电 相关信号外部施加，并且预充电部分切断电源电压而不被施加到一对位线; 以及位线浮动防止部件，用于以缺陷补偿地固定一对位线的电位值，使得防止单元电源电压被施加到半导体存储器件的存储器访问模式下的缺陷的位线对， 使得像预备电流故障那样的硬型缺陷可以被修复，而不管预充电控制信号的逻辑状态如何，从而降低了半导体存储器件中的缺陷的发生概率。