公开(公告)号：US10964992B2

公开(公告)日：2021-03-30

申请号：US16186103

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Henning Braunisch ,  Gilbert W. Dewey ,  Telesphor Kamgaing ,  Hyung-Jin Lee ,  Johanna M. Swan

IPC: H01P1/213 ,  H01P3/127 ,  H01P5/103 ,  H01P3/10 ,  H01P3/16 ,  H01P5/107 ,  H01P3/12 ,  H01P5/08

Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.

公开(公告)号：US20210082822A1

公开(公告)日：2021-03-18

申请号：US16573943

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic interposer may be formed comprising an upper section, a lower section and a middle section. The upper section and the lower section may each have between two and four layers, wherein each layer comprises an organic material layer and at least one conductive route comprising at least one conductive trace and at least one conductive via. The middle section may be formed between the upper section and the lower section, wherein the middle section comprises up to eight layers, wherein each layer comprises an organic material and at least one conductive route comprising at least one conductive trace and at least one conductive via, and wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and thinner than a thickness of any of the layers of the lower section.

公开(公告)号：US20200315052A1

公开(公告)日：2020-10-01

申请号：US16402055

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Johanna M. Swan ,  Georgios Dogiamis ,  Henning Braunisch ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Richard Dischler

IPC: H05K7/14 ,  H01P3/16 ,  H05K1/02 ,  H01P5/12

Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US20190356033A1

公开(公告)日：2019-11-21

申请号：US16014036

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan

IPC: H01P3/16 ,  H01L23/66

Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

公开(公告)号：US20190318993A1

公开(公告)日：2019-10-17

申请号：US16469084

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US20190259705A1

公开(公告)日：2019-08-22

申请号：US16335845

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Henning Braunisch ,  Krishna Bharath ,  Javier Soto Gonzalez ,  Javier A. Falcon

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US20190089409A1

公开(公告)日：2019-03-21

申请号：US16196367

申请日：2018-11-20

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios Dogiamis ,  Henning Braunisch ,  Hyung-Jin Lee ,  Richard Dischler

IPC: H04B3/52 ,  H04B3/56 ,  H04B1/52

Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.

公开(公告)号：US10187998B2

公开(公告)日：2019-01-22

申请号：US15621403

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Henning Braunisch

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42

Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

公开(公告)号：US10054737B2

公开(公告)日：2018-08-21

申请号：US15352520

申请日：2016-11-15

Applicant: Intel Corporation

Inventor： Mauro J Kobrinsky ,  Henning Braunisch ,  Shawna M. Liff ,  Peter L. Chang ,  Bruce A. Block ,  Johanna M. Swan

IPC: G02B6/12 ,  G02B6/42 ,  H04B10/40 ,  H04B10/25 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L21/56

CPC classification number: G02B6/12004 ,  G02B6/12 ,  G02B6/30 ,  G02B6/4214 ,  G02B6/4257 ,  G02B6/428 ,  G02B2006/12061 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/167 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83048 ,  H01L2224/83102 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/15312 ,  H04B10/25 ,  H04B10/40 ,  H04B10/801 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.

公开(公告)号：US09992859B2

公开(公告)日：2018-06-05

申请号：US14866693

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/02 ,  H01P3/026 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.